Electronic conferences seem to be of two varieties—those that introduce several innovative products and methodologies and others that enhance existing solutions. The 42nd Design Automation Conference (DAC), held in Anaheim, CA in June, fits into the second category. Building upon an existing base of design tools and products is not a bad thing, however. Very often, improving upon what has been previously introduced marks the point at which those products truly become usable for the mainstream electronics community. Following are some of the hot topics that garnered a lot of attention at DAC. Note that all of them (semiconductor IP, design for manufacturability, and electronic system level design) have been on the microelectronics industry's "hot topic" list for several years, making them prime candidates for tools and methodologies that make them easier to include in chip designs.

Initially released in August of 2003, QIP reduces the time typically required to make an IP purchase decision and to integrate SIP into a chip. The Metric helps the IP vendor and IP consumer (integrator) communicate based on an objective foundation. Besides setting up the basis for measuring a core's characteristics against an industry-approved list of attributes, the standard provides a view of the IP vendor's general approach to IP development. This levels the playing field for vendors and allows an integrator to evaluate similar cores from competing vendors.

The new version of the Metric is easier to use than its predecessor and is more streamlined. New in 2.0 is a vendor qualification worksheet, applying to all IP from a vendor, covering development processes, quality assurance, design and support infrastructure, and other general corporate capabilities. This version also has simpler IP-qualification metrics covering documentation, deliverables, and information specific to the IP integrator as well as IP development practices. QIP Metric 2.0 includes the newly added vendor assessment and the requirements for Soft IP have been restructured and revisited. Legacy worksheets, taken from the previous QIP Metric version, include software IP, verification IP, and hard IP worksheets, including digital and analog/mixed signals—these will be updated in future QIP Metric releases.

Cadence Design Systems, Freescale Semiconductor, LSI Logic, Philips, and STMicroelectronics will participate in the beta testing of 2.0 and, going forward, will require that IP vendors provide scores when delivering new IP cores. Mentor Graphics and Chipidea, IP vendors, have been providing scores to their customers based on the Alpha version of the QIP Metric.

DAC had several events covering DFM. Naveed Sherani, CEO of Open-Silicon, chaired a panel of representatives from Ponte Solutions, KLA-Tencor, Magma Design Automation, Xilinx, PDF Solutions, and Clear Shape Technologies discussing "DFM Rules," future trends in DFM that will have to be addressed for sub-100nm chips to be viable. Several DAC papers covered various aspects of DFM, including: how design and cell compensation can help offset line-width variation during chip processing; special routing technology to reconcile the interdependency between nanometer lithography and physical design; and the economic benefits of DFM and how to measure them.

During a private presentation, Synopsys showed a very nice chart of the four types of defects that affect chip yield—random, systematic, printability, and parametric—and the mechanisms used to minimize yield loss for each one (Figure 1).

Figure 1:  This chart shows the four types of defects that affect yield. For each one, there are several techniques chip designers and process engineers can use to reduce yield loss. (Courtesy Synopsys)

Synopsys also described the three key components of successful DFM: convergence, accuracy, and turnaround time. Convergence requires a bilateral information flow between the chip designer (design intent) and manufacturing providers (silicon and mask manufacturing information) all the way from system design through chip packaging and test. Accuracy depends on good modeling of the design and process and the ability to compensate for process variations. Fast turnaround is based on good software tools and well thought-out design and operations flows.

TSMC also contributed to the DFM activity at DAC with the announcement of the free Yield Plus and fee-based Yield Pro, two process-based DFM toolkits to increase yield and accelerate production ramp-up. Developed by TSMC and its EDA partners and optionally implemented by the designer, Yield Plus includes Action-Required rules, Recommended Advisories (extension of layout design rules for increasing yield) and Guidelines for chip design that the designer can follow during chip layout that can enhance chip performance and reduce Optical Proximity Correction (OPC) cycle and mask-making times. The tool also includes DFM utilities to implement the rules and advisories.

Implemented by TSMC during some design-implementation tasks as well as during chip manufacturing, Yield Pro includes a variety of services, including:

• Lithography Process Check (LPC) to simulate from the GDS-II file what the on-wafer pattern will look like (Figure 2)
• Yield Sensitivity Analysis (YSA) to analyze yield sensitivity during each of the process steps and to check yield enhancement by implementing DFM recommendations
• Package Modeling to evaluate the thermal, mechanical and electrical characteristics of a chip's package
• Scan Diagnostic, to reduce chip debug time and to accelerate the movement of a design to production.

Figure 2:  By simulating the on-chip pattern from the chip's layout (GDS-II) file, TSMC's LPC service can identify potential yield-loss mechanisms, such as opens due to metal pinching and shorts due to metal bridging. (Courtesy TSMC)

TSMC's new Reference Design Flow 6.0 also addresses DFM by integrating mature DFM rules into the flow. Other new features in Flow 6.0 addressing power-conscious design include support of voltage scaling for multiple voltage islands to reduce active and leakage power, and power gating of library cells using fine-grain (one transistor per cell) multiple-threshold CMOS (MTCMOS) transistors to reduce leakage current in sleep mode by around 90%.

Magma Design Automation introduced the company's new Blast Yield, a design-for-manufacturability (DFM) and design-for-yield (DFY) tool for chip designs at 90nm and below. Integrated in Magma's RTL-to-GDSII implementation flow, Blast Yield helps improve yield and accelerate complete design closure through concurrent optimization of timing, area, power, noise and yield. This marks Magma's inclusion of yield as a design parameter along with the traditional timing, area, power, and signal integrity and recognition of the need to consider manufacturability and yield issues early in during chip design.

Blast Yield features include functional cell-yield optimization (yield is concurrently optimized along with other design parameters) along with yield-aware technology mapping and cell sizing to ensure optimum selection of logic cells and sizes that will meet timing specifications and produce better yield. The tool also includes critical area analysis to identify failure probability due to random particulate defects that cause shorts and opens in wires. Blast Yield performs wire spreading, both on a global and detailed basis, or wire sizing based on the critical area associated with random defects. According to Magma, the result is a wiring topology with reduced critical area, resulting in lower failure probability. Wire spreading can be done both in global routing and detailed routing, and viewed graphically through the critical area map.

Another highlight of Blast Yield is an OPC-aware routing capability that uses fast and accurate OPC simulation technology to predict potential problems and makes the routing topology more OPC compliant. Blast Yield also provides support for advanced DFM-rules including redundant via insertion, short-edge rules and extended end-of-line rules.

DK4 lets designers go from large software models directly to FPGA implementations with optimized EDIF netlists, synthesizing complete systems including complex algorithms, system interfaces and multiple clock domains. The new version of DK lets designers better utilize the architecture-specific embedded ALU features and DSP blocks in very high density FPGAs such as Altera's Stratix II and Xilinx's Virtex 4. DK4 support now also extends to Xilinx's high-density Spartan 3E and the lower power Spartan 3L FPGAs.

Addressing the growing verification requirements of SoCs, Carbon Design Systems announced VSP (Virtual System Prototyping), a desktop-based software-only tool that lets designers combine multiple abstraction levels early in a design. VSP lets the designer work with C and SystemC behavioral models, legacy RTL, IP cores, and transaction-level and instruction-level models to validate software, with rapid execution, on a virtual system prototype long before a complete RTL model of the hardware is developed (Figure 3). Carbon claims that VSP will uncover functional bugs that behavioral models alone will miss, including problems with memory maps, cycle latency, bus arbitration, cache coherency, interrupt handling, and synchronization to the SoC design specification.

Figure 3:  The VSP functional validation platform lets designers validate multiple levels of abstraction together including C, SystemC, RTL, IP cores, transaction-level, and instruction-level models. VSP can execute billions of cycles and boot embedded operating systems, all with desktop software.

Although VSP does not have its own processor models, it does link to ARM's SystemC-compliant MaxSim instruction-set simulator and also has links to fast processor models from other companies. Not available at this time, in the future Carbon also plans to provide silicon IP libraries with VSP.

Jim Lipman is currently Vice President, Client Services for Cain Communications, specializing in the development and implementation of communication and marketing services programs for companies serving the semiconductor, silicon-IP, EDA, and other high-tech electronics-industry segments. Jim's experience includes chip-design R&D, marketing, marcom, consulting, technical editing, technology training, and on-line publishing of technical content for engineers. His email address is jlipman@caincom.com.