Design Article

EDA Tools Bolster Chip Recovery

Jim Lipman

5/26/2004 12:00 AM EDT

While there are several reasons why the IC industry is coming out of its worst recession in history, one that stands out is EDA support for both design tools and design methodology. During the economic downturn, EDA vendors devoted large amounts of time and money to helping chip vendors operate more effectively when their business picked up. That time has arrived. Design-for-manufacturability (DFM), integrated tool suites addressing complete design closure, chip-test enhancement, and support for new design implementations are some of the key areas in which EDA tools are increasing chip-vendor profitability, during chip design and in manufacturing operations.

Enhancing Manufacturing Yield

EDA companies, like their IC-vendor counterparts, realize that an important component of reducing chip cost is addressing DFM issues. It is not enough to support the initial design of a chip that meets design specifications—EDA tools must also be in place to assist the transition from design to volume manufacturing of the chip. To accomplish this goal, EDA vendors are working very closely with silicon vendors to assure that the design tools and flows they offer work efficiently with foundry processes, cell libraries, silicon IP, and work flows.

For example, TSMC has developed a design reference flow (Reference Flow 4.0) that concentrates on backend, post-synthesis IC design. This recommended design flow works with both Cadence and Synopsys tool suites (Figure 1), and addresses physical design, extraction, signal-integrity, and timing-analysis operations. Reference Flow 4.0 and the associated EDA tools also support several yield enhancement techniques including process-variation modeling, the use of redundant vias, and reduction of intra-chip metal variation through the use of dummy metal insertion to increase copper uniformity across a chip. The latter operation reduces timing variation, with its associated yield loss, due to uneven copper thickness on the chip.

Figure 1: The TSMC design reference flow with Cadence and Synopsys tool suites

EDA vendors have also developed tools to support reticle-enhancement techniques (RETs), such as optical proximity correction (OPC) and phase-shift masks (PSMs). RET serves two purposes—to increase the life of existing photolithographic equipment as technology nodes shrink, and to increase chip yield by improving the integrity of images that are printed from photomask to the silicon wafer.

Integrated Tool Suites

As process nodes have transitioned from 180 nm to 130 nm and beyond, the tools to deal with silicon designs at these geometries have had to improve significantly in several ways to deal with increasing design turnaround time—60% for each technology generation, according to Magma Design Automation (Figure 2). Among the most critical areas are timing closure, signal-integrity analysis, power analysis and integrity, chip testability and, of course, DFM. Also significant is the lowering of the barrier between front-end (though logic synthesis) and backend design (physical implementation), which has resulted in a close coupling between synthesis and place-and-route (P&R) operations. Due to the complexity of physical design at 130 nm and below, synthesis tools must have knowledge of a chip's physical layout to be able to adequate synthesize the design from an HDL level. So-called physical-synthesis tools are quickly replacing standalone floorplanning tools as a means of importing physical knowledge into logic-synthesis tools, often as part of fully integrated, single-vendor, RTL-to-layout tool suites.

Figure 2: The time it takes to design a chip increases significantly with each new generation of silicon process technology. This increase is due to several factors, including higher chip complexity, more stringent design specifications, and the stronger influence of silicon parasitics.

The ability to employ different design tools from several vendors at various points during the design flow becomes much more difficult as design complexity increases and process nodes shrink. Leading-edge chip designs have gone beyond a strong emphasis on primarily timing closure—convergence between the timing employed in the logic-synthesis process and what is extracted from physical layout. Chips now must achieve design closure that, along with timing, includes meeting power, signal-integrity, and other design specifications. Tool suites often include integrated tools for analyzing power dissipation, both static and dynamic, signal-integrity, and design-for-test (DFT). In addition, these suites often employ tools to help designers correct design problems that they may have discovered during design verification.

Enhancing Test

Considering chip manufacturing test during design can significantly decrease test cost, often a significant portion of total chip cost for complex ASICs and SoCs. Increasing chip yield and test throughput serves to decrease the per-chip test cost. EDA tools enhance chip test through many mechanisms, including efficient built-in self-test (BIST) of silicon cores, test-set compaction (since test throughput is inversely proportional to test time), and targeting the automatic test equipment (ATE) on which the chip will be tested. Close coupling of DFT, on the design side, and tester parameters, on the ATE side, results in faster and more efficient test-program development, leading to faster time-to-manufacturing and less expensive testing. All of the major EDA tool-suite vendors have programs in place with ATE manufacturers to help achieve close DFT/ATE coupling.

Alternative Design Implementations

The past year has seen increased interest in structured and platform ASICs—silicon implementations that allow the designer to configure a chip, during design, by personalizing a subset of the total photomask set. These configurable chips address the mid-volume range of chip manufacturing and mid-to-high performance requirements, falling between low NRE, high unit-cost FPGAs and high NRE, low unit-cost, long design time ASICs. EDA tool vendors, such as Synplicity, are recognizing the viability of structured and platform ASICs and are optimizing their tools, targeting specific architectures such as NEC's ISSP, for designing these types of chips.

About the Author

Jim Lipman is currently the President and Editor-in-Chief of SemiView Inc., a new company providing business, financial, and technology analysis, research, and editorial information for the rapidly growing Application-Adaptable Integrated-Circuit (AAIC) industry. His job experience includes chip-design R&D, marketing, marcom, technical editing, and on-line publishing of technical content for engineers.

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