Design Article
Signal Integrity Sign-Off Verification
Rajit Chandra
5/6/2002 12:00 AM EDT
The number of silicon failures caused by undetected and unresolved signal integrity (SI) violations is rising dramatically. This is because SI effects are becoming increasingly significant as deep sub-micron (DSM) geometries continue to shrink and functional density—the number of transistors on a device—continues to rise.
Excessively conservative design practices result in device performance that is significantly below the silicon's full potential. This is simply not an option in today's highly competitive marketplace. The alternative—using conventional design and verification tools—involves numerous time-consuming and costly design iterations, resulting in failed schedules.
The fundamental issue is that timing closure and functional verification cannot be considered to be complete until post-layout SI effects have been fully accounted for. The problem is that SI effects like crosstalk (both noise and timing), voltage (IR) drop, and electromigration have complex interdependencies. However, conventional point-solution design tools do not have the capability to consider all of these effects and their interrelationships concurrently. This problem is exacerbated by the fact that post-layout SI sign-off verification requires a greater level of accuracy than the SI analysis performed during the implementation phase. However, increasing the accuracy of the analysis to account for transistor-level effects results in capacity limitations and excessively long run times when using conventional tools.
This article introduces some of the more common SI effects that need to be accounted for during implementation and—to a far greater level of accuracy—during post-layout sign-off verification. Also discussed is an innovative new approach to SI sign-off verification.
Common Signal Integrity Effects
Early IC implementation technologies were cell delay dominated. That is, delays associated with the logic elements far outweighed delays associated with the interconnect. By comparison, today's DSM implementation technologies are interconnect delay dominated. Resistive and capacitive (RC) interconnect delay effects that used to be third or fourth-order in terms of relative magnitude and significance are now first-order, which means that any changes in signal behavior can have a major effect on the quality of the design.
Increased Sidewall Capacitive Coupling
In the case of early IC implementation technologies, the aspect ratio of tracks was such that their width was significantly greater than their height (Figure 1a). However, as feature sizes continue to shrink, the processes used to create these devices result in track aspect ratios in which height predominates over width (Figure 1b).
The result is a dramatic increase in coupling capacitance (CXCOUP) between the sidewalls of adjacent tracks relative to the substrate capacitances CAREA (track base to substrate) and CFRINGE (sidewall to substrate). Furthermore, the high integration densities associated with today's devices—which can support as many as eight metalization layers—results in significant capacitive coupling between adjacent layers. This is represented by CCROSSOVER (Figure 2).
The combination of these factors leads to a tremendous increase in the complexity of crosstalk noise and timing effects as discussed below.
Crosstalk-Induced Glitches
When signals in neighboring wires transition between logic values, the coupling capacitance between the wires causes a transfer of charge. Depending on the slew of the signals (the speed of switching in terms of rise and fall times) and the amount of mutual crosstalk capacitance (CXTALK) there can be significant crosstalk-induced glitches (Figure 3).
In this example, a transition on a fast aggressor net causes a glitch to be presented to the input of the load/receiver of an adjacent victim net. Of course this illustration presents a very simplistic view. In reality, each track may be formed from multiple segments occupying multiple levels of metalization. Thus, the resistances (RWIRE1 and RWIRE2) and capacitances (CWIRE1 and CWIRE2) will each consist of multiple elements associated with the different segments. Similarly, the mutual coupling crosstalk capacitance (CXTALK) may consist of multiple elements. Some of these will be equivalent to CXCOUP if segments of the aggressor and victim nets are neighbors on the same metalization layer, or CCROSSOVER if the aggressor and victim nets cross each other on adjacent layers (see Figure 2).
The example glitch illustrated in Figure 3 represents only one of four generic possibilities based on the fact that a rising or falling transition on the aggressor net may be coupled with a logic 0 or logic 1 on the victim net (Figure 4).
If the ensuing low noise or high noise glitches on the victim net cross the input-switching threshold of its load/receiver, a functional (logic) error may occur. In some cases this error may manifest itself as an incorrect data value that is subsequently loaded into a register or latch. In other cases, the error may cause a latch to perform an unintended load, set, or reset.
The low undershoot and high overshoot glitches on the victim net pose a different problem, because they can cause undesirable charge carriers to be trapped in the transistors forming the logic gates, which can degrade circuit performance. Although these effects—commonly known as hot electron effects—are not a major threat in the context of current IC implementation technologies, they will become increasingly significant as device geometries progress into the ultra-DSM realm.
Crosstalk-Induced Timing Errors
The situation becomes even more complex when simultaneous switching occurs on both the aggressor and victim nets. For example, in the case of opposing transitions, the signal on the victim net may be slowed down (Figure 5).
If the signal on the victim net were transitioning in isolation, it would take a certain amount of time to cross its load/receiver's switching threshold (which, for the purposes of these discussions, may be assumed to be 50% of the value between a logic 0 and a logic 1). However, the glitch caused by a simultaneous transition on the aggressor net holds the victim's signal above the load/receiver's switching threshold for an additional amount of time. This can result in a downstream setup violation.
An alternative scenario occurs when a transition on the victim is complemented by a simultaneous transition on the aggressor in the same direction, in which case the signal on the victim may speed up (Figure 6).
In this case, the glitch caused by a simultaneous transition on the aggressor net causes the victim's signal to cross the load/receiver's switching threshold earlier than expected. This can result in a downstream hold violation.
Of course the examples shown above are somewhat simplistic. In real-world designs, each victim net may be affected by multiple aggressors (Figure 7). Accurate analysis of today's DSM designs requires each aggressor's contribution to be individually accounted for and analyzed.
Voltage Drop Issues
DSM devices are prone to voltage drop (often referred to as IR drop) effects caused by the resistance associated with the network of wires used to distribute power and ground from the external pins to the internal circuitry. Voltage drop effects are becoming increasingly significant, because the resistivity of the power and ground tracks rises as a function of decreasing feature sizes (track widths). Also, the rising clock rates seen in modern devices cause a corresponding increase in dynamic power requirements, resulting in dynamic IR drop across power nets.
The input-to-output delays across a logic gate increase in a non-linear manner as the voltage supplied to the gate is reduced, which can cause the gate to miss its timing specifications. There is also an increase in the interconnect delays associated with underpowered gates. Furthermore, a gate's input switching thresholds are modified when its supply is reduced, which causes the gate to be more susceptible to noise. Last but not least, victim nets driven by underpowered logic gates may become more susceptible to glitches caused by aggressor nets.
Reliability Issues (Electromigration, Wire Self-Heat, ...)
Electromigration (EM) occurs when the current density (current per cross-sectional area) in power or signal lines is too high. In the case of power and ground tracks, EM effects are DC (direct current) based. The so-called "electron wind" induced by the current causes metal ions in the track to migrate. This migration creates "voids" in the "upwind" direction, while metal ions can accumulate "downwind" to form features called "hillocks" and "whiskers."
This form of power and ground EM can cause major functional errors to occur, because the voids can eventually lead to open circuits while the hillocks and whiskers can cause short circuits to neighboring wires. EM can also cause timing problems, because the increased track resistance caused by a void can result in a voltage drop, which can in turn cause increased delays and noise susceptibility as discussed above.
In the case of signal lines, EM effects are AC (alternating current) based and do not result in any net migration of metal ions. The two main forms of signal EM are referred to as the wire self-heat and hot electron effects. Wire self-heat occurs when the current density is too high. The resulting heating effect causes the affected tracks (both cell-to-cell interconnect and tracks inside cells) to expand and contract, which degrades the reliability of the design. The hot electron problem refers to the case where carriers are injected into—and become trapped in—a transistor's channel. This distorts the field used to control the transistor, which results in performance degradation. Sufficiently energetic electrons can exhibit tunneling effects that break down the transistor's oxide layer and can cause a permanent breakdown. One contributing factor to the hot electron problem is the crosstalk-induced overshoot and undershoot glitches as illustrated in Figure 4.
Implementation Versus Sign-Off Verification Solutions
The entire chip design process may be visualized as comprising three main stages: planning, implementation, and sign-off verification (Figure 8).
The planning stage may be considered to include prototyping, floorplanning, and simulation. Implementation includes synthesis, optimization, placement, routing, clock and power design, parasitic extraction, timing analysis, and signal integrity analysis. Sign-off verification includes signing off on signal integrity issues based on the highly detailed information that is now available. Although SI analysis appears in both the implementation and sign-off verification phases, the requirements for each phase are significantly different.
SI effects are becoming increasingly significant as deep sub-micron (DSM) geometries continue to shrink and the number of transistors on a device continues to rise. The result is that silicon failures caused by undetected and unresolved signal integrity (SI) violations are increasing dramatically.
The fundamental issue is that timing closure and functional verification cannot be considered to be complete until post-layout SI effects have been fully accounted for. SI effects like crosstalk (both noise and timing), voltage drop (IR drop), and electromigration have complex interdependencies. To effectively address SI verification, a solution must consider all of these effects and their interrelationships concurrently, with a greater level of accuracy than the SI analysis performed during the implementation, and without suffering from capacity limitations and excessively long run times.
About the Author
Dr. Rajit Chandra is Vice President of Technology at Magma Design Automation. Prior to Magma, he was the co-founder and VP of Technology at Moscape, which specialized in Electronic Design Automation Tools for both gate- and transistor-level electrical-integrity verification. Dr. Chandra has several years' experience working in IC design teams and in developing EDA technology and industry standards necessary for efficient chip design. He is currently working on technologies that allow design flows to reduce iterations while implementing quality designs that are free of signal-integrity issues.
