This year's Design Automation Conference in Las Vegas had its share of exciting new products. Unfortunately, the economic downturn in the electronics industry forced many people to stay home who would normally be at the show. If you're one of those people, you missed a good DAC with respect to both exhibits and technical sessions.

Trying to cover all of the DAC and pre-DAC announcements in one wrap-up article is an impossible task. Instead, I've chosen some of what I consider as interesting products in hot areas. This is not an all-encompassing wrap-up; it includes only a few companies and some of the products they exhibited and discussed at the show.

Timing Closure
Design closure is a topic that has been in the hot category for the last few years. We define design closure as the ability to design a chip with a minimum of iterations between logic synthesis and physical implementation (place-and-route operations). Most EDA vendors try to achieve closure by increasing the coupling between the synthesis and physical-implementation operations, often by introducing knowledge of the physical design into logic synthesis or coupling the synthesis/placement tasks. Four companies—Monterey Design Systems, Magma Design Automation, Synopsys, and Get2Chip—announced new or enhanced timing-closure software at DAC.

Monterey System-Driven Physical Design (SDPD) methodology couples three of the company's design tools—IC Wizard, Sonar, and Dolphin. SDPD moves critical physical details up to the early planning stages, letting you work with a top-down, constraint-driven design methodology. IC Wizard provides hierarchical design planning, at the block level, from architectural exploration through physical implementation. Sonar gives you physical-prototyping capabilities. Dolphin does optimized, physical implementation of complex chip designs. You create optimized floorplans using early physical data, evaluate the plans using physical prototypes, and apply automated tools to implement the physical design.

Magma enhanced its flagship Blast Fusion tool and introduced a new design-planning tool, Blast Plan. Working with other Magma tools, Blast Plan provides a suite of top-down planning and design capabilities to streamline the hierarchical planning and design of very large chips and SoCs within a single design environment. These capabilities help eliminate the cumbersome and error-prone data transfers between point tools in traditional design flows. In this regard, Blast Plan performs some similar functions as does Monterey's SDPD—putting constraint-driven chip design into a common design environment. Magma also has an enhanced version of its Blast Fusion physical-design software system. The new Blast Fusion runs faster, uses less memory, and boasts advanced clock synthesis, power planning, new router features, and automated support for complex manufacturing rules.

Synopsys has added two optional modules to its Physical Compiler physical-implementation tool—Route Compiler and ClockTree Compiler. Of particular interest is Route Compiler, an area-based, timing-driven, standard-cell router that provides timing- and signal-integrity-driven routing. Route Compiler uses a constraint-driven algorithm that does detailed routing for short nets during global routing. This capability reduces via counts and shortens wires, leading to better manufacturing yield and, in some cases, higher chip performance. The company also added signal integrity to the synthesis cost function to address crosstalk problems throughout the design flow. Signal-integrity prevention and repair features, available during physical implementation, include crosstalk-driven placement, net-isolation techniques, buffer insertion, driver sizing, and variable width and spacing.

Get2Chip's TOPOMO is a physical compiler that models chip topology, while concurrently looking at the effects of architecture, block sizes and locations, and interconnect impact. The tool combines block partitioning, block placement, global routing, and logic synthesis, combining physical views with synthesis early in the design process. TOPOMO outputs a timing-accurate netlist, placement directives, timing directives, global-routing suggestions, and a clock-tree topology to physical-synthesis and place-and-route tools, reducing the number of iterations between back-end and front-end design.

RTL Analysis and Verification
In search of one of chip-design's holy grails—RTL signoff—EDA and chip companies are putting more efforts onto design analysis and verification at the register-transfer level. However, the task is difficult, since RTL code has architectural knowledge, but no inherent structural knowledge. This means that a design's RTL description does not have knowledge of the design's gate-level structure or cell-library attributes, both of which add to the knowledge a tool needs to accurately analyze and verify a design. Nevertheless, some EDA vendors have developed unique tools and methodologies to attack RTL design.

Newcomer Atrenta has a unique way of addressing verification with its SpyGlass tool. SpyGlass has a look-ahead capability that considers downstream-tool constraints inherent in design, synthesis, test, and manufacture tools and operations, and pinpoints any potential problems in the RTL source code. This function is like a higher-level linting—whereby linting tools find HDL syntax, semantics and, sometimes, design-style errors, SpyGlass spots problems that will crop up during subsequent tool operations. SpyGlass comprises various engines that do language analysis, synthesis, and gate-level exploration, reporting downstream tool violations and linking these problems back to the RTL source code. The tool comes with rule decks covering coding style, design practices, design portability, reusability constraints, design-for-test, and other rules based on the Reuse Methodology Manual; you can also use custom rules with the tool.

Another startup, @HDL, is out with two new tools, @Verifier and @Designer. Both tools use a hybrid verification technique combining static (formal model checking) and dynamic (intelligent-random) verification technologies with system-level RTL code analysis and debugging for Verilog users. @Verifier uses automatic property generation for formal model checking. After RTL Rule checking, the tool automatically identifies RTL design elements, such as finite-state machines (FSMs), FIFOs, and flip-flops, extracts the properties each element needs for verification, and uses static and dynamic techniques to prove these properties. Finite State Machine deadlocks, false-path logic errors, and unreachable states are the types of problems for which @Verifier checks.

@Designer, an HTML-based browser tool with a search-engine and automatic RTL design-element inference capability, lets you do debugging at the transaction and protocol level. The tool lets you graphically debug at the system level (bus read / bus write) while the design works at the signal level (1s and 0s). @Designer's features include RTL source-code static analysis and high-level viewing of a design's simulation, including results such as multi-clock domain analysis and synchronization, and FSM state visualization.

Real Intent has enhanced its RTL formal-verification tool, Verix, to work on designs hierarchically. The tool combines the formal results of lower blocks to formally verify higher blocks. You verify lower-level blocks once, then the tool only does incremental analysis at the next level of hierarchy. This feature gives Verix much greater capacity and users higher productivity than with a flat formal-verification tool. The tool reads RTL code and, with designer intent in mind, checks for design problems such as conflicting assignments, non-resettable flip-flops, and range violations.

High-Level Analysis and Verification
Increasing design complexity and shrinking design windows are pushing designers to even higher levels of design—either into system-level language descriptions, primarily with C/C++ or derivatives, or with supersets of HDLs. Pre-HDL verification is of particular interest to designers, since finding problems prior to generating Verilog or VHDL means time (and money) saved later.

Co-Design Automation's system-level simulator, SYSTEMSIM, now comes with verification capabilities. The combined performance simulation and verification environment does away with external testbench utilities. Verification automation functions execute directly from SYSTEMSIM, resulting in a 4x-performance improvement over verification functions tied to a simulator through a PLI. Embedded functional-test automation capabilities in SYSTEMSIM detect complex corner-case issues with fewer simulation cycles and reduced testbench-coding. Capabilities include constrained-random-test generation, functional-test coverage, assertion and property checks, data manipulation, and queuing functions. Co-Design also enhanced the SUPERLOG language to support greater verification facilities, letting designers use Verilog for testbench specification. SUPERLOG now has advanced programming constructs to a Verilog base, system functions such as advanced interfacing for bus-functional models, and many object-oriented style features.

C Level Design's System Compiler Designer is a design environment for C/C++ hardware Design. The tool lets you use HDL-like features for design and debugging and helps automate the verification of post-synthesis results against the original C/C++ design. System Compiler Designer also includes support for C/C++ post-simulation graphical analysis with industry-standard VCD waveform viewers. Along with these capabilities, the design environment also has the CycleC StyleChecker analyzer, which does a comprehensive compile-time analysis of the C/C++ design, checking for coding violations that would result in inefficient or incorrect HDL output during synthesis.

Addressing architectural design is Icinergy's SOCarchitect. The physical-planning tool brings a design's physical aspects, including logical connectivity, to the architectural level giving the designer a "design view" prior to RTL-code generation. SOCarchitect takes early design data to produce a blueprint you can use to explore different design architectures and floorplans. As you finish block designs, you update SOCarchitect with more complete and accurate data for these blocks. Tool capabilities include block partitioning; port and block floorplanning; area management; technology re-targeting; congestion, power, and timing analyses; integration to back-end flows; and tcl scripting.

Configurable Cores
Configurable processing cores, both RISC and DSP, are gaining in popularity as technology vehicles to optimize chips both from performance and cost viewpoints. The ability to modify a processing engine's function lets you differentiate the chip in which the processor is used, and adjust to changing standards in rapidly evolving market segments such as communications and networking. Vendors made significant product enhancements for both DSP and RISC cores at DAC this year.

Improv Systems' second-generation version of the company's Jazz DSP core, Jazz 2, has a 16-bit option to complement the existing 32-bit architecture. The 16-bit core has lower power dissipation and a smaller core size (approximately 50K gates vs. around 100K gates for Jazz 1). The core also features enhanced processor architecture, better memory, and improved power-management features. For co-processor applications, Improv designed Jazz to work with microprocessor-based chips through ARM's AMBA/AHB and MIPS' PI bus interfaces. The company's automated processor-configuration tool, Jazz Composer 2 includes instruction-extension composing, for user instructions, and what Improv calls Programmable System composing, to help you design systems with multiple processors.

Also addressing multi-processor chips is Tensilica's Xtensa IV architecture. With the new microprocessor architecture, you can design and optimize each processor in a multiprocessor chip for a specific task (heterogeneous functionality), enhancing total chip optimization. Heterogeneous processor functionality also reduces the need for user-defined logic and, in some cases, coprocessor cores, reducing chip size, cost, and development time. Also reducing development time is that you use a common processor-development environment for all Xtensa processors on a chip.

Another significant DSP-core product line comes from BOPS. The company announced low-power cores targeted for the mobile wireless market. The cores have performance ranging from 1000-4000 MIPS (16-bit RISC equivalent MIPS) and feature an ultra-low power dissipation of 0.01mW/MIP. You can use the MoCARAy, MICoRay, and WirelessRay cores as thread-co-processors to ARM, MIPS, and other low-power microprocessors. Each core is configurable for new standards, specialized control functions and other differentiating features, and system-specific interfaces.

Analog/Mixed Signal Design
With analog functions becoming increasingly important for SoCs, EDA tools for analog/mixed-signal designs are critical items for SoC designers. Unfortunately, the advances EDA vendors are making in analog/mixed-signal tool development lag far behind those targeted at digital design. However, there were two significant products at DAC, one covering test and the other analog-circuit synthesis, for engineers working on analog or mixed-signal chips.

Addressing the difficult problem of analog synthesis, Neolinear's automated synthesis software, NeoCircuit v1.0, helps designers size and verify analog-circuit topologies. The tool works with all simulation/verification environments to size circuits relative to critical design specifications. NeoCircuit synthesizes any topology and let you evaluate specifications such as settling time, IIP3, quiescent power, slew rate, DC gain, and static power for different topologies. You can also view trade-off curves that show a range of design alternatives. After NeoCircuit synthesizes a circuit, you can use NeoCell, available from Cadence Design Systems, to automate layout.

Another difficult and expensive problem for designers is testing analog/mixed circuits. Fluence has a unique solution to this problem for one class of circuit, analog-to-digital converters (ADCs). The company's ADCBIST technology and ADCBIST Developer tool reduce the time and cost of embedded-ADC production testing without impacting functional on-chip circuitry. Using an all-digital histogram generator, ADCBIST collects data from the ADC-under-test and uses the data to compute parameters relating to the ADC's performance. The histogram-based data collection uses less memory, is faster, and is inherently more immune to noise than traditional analog-measurement techniques. The resulting histograms provide numerical results for many ADC parameters, including differential non-linearity, integral non-linearity, offset, gain, transfer function, and missing codes.

ADCBIST Developer lets you select the BIST measurements you need to test a specific ADC before silicon and then verify the ADC's performance through simulation. The software comprises a stimulator and data-acquisition import feature, ADC behavioral modeling capability, and histogram processing for the ADC. When you use ADCBIST Developer with ADCBIST, you can transfer the simulation results directly to digital-ATE test programs, saving test-development time.

One for the Road
Although it does not fit into any of the previously discussed hot categories, one more DAC announcement is worth reviewing—the X Architecture. Simplex Solutions and Toshiba have developed a new semiconductor architecture that makes use of diagonal interconnects on chips. A diagonal path between two chip nodes will often be shorter than an interconnect path comprised of traditional Manhattan, or right angle, wire structures. This means that diagonal routing can result in reduced interconnect lengths, higher speed, and lower power dissipation.

Several leading semiconductor companies are launching a five-year initiative aimed at accelerating the availability and fabrication of the X Architecture. The X Initiative consortium is comprised of representative companies involved with silicon IP, EDA products, IC design services, photomask production, and semiconductor equipment and manufacturing.