The Custom Integrated Circuits Conference (CICC), taking place in San Diego from May 6-9, continues to be the premier conference for chip designers. One reason for CICC's continuing success is that the emphasis is on "conference", with four days of interesting and informative educational and technical sessions. These sessions are complemented by a relatively small number—around two dozen—of exhibits by key design and EDA companies.

"Fueling the Communications Revolution" is the theme of this year's CICC, reflecting the explosion of network and wireless communications design throughout the electronics industry. The communications theme is evident in many of the papers throughout the conference's educational sessions, technical paper sessions, and panels. Of particular interest are two of Sunday's educational sessions, IC Design for Wireless Applications and Circuit Design of Optical Fiber Communications, and a Tuesday afternoon panel, Will the Real Network Processor Please Stand Up? The educational sessions include technically rich lectures on RF circuit design, low-phase noise oscillators, high-speed optical interfaces, optical receiver and transmitter design, and SiGe bipolar technology. The network processor panel features industry leaders discussing today's network processor chips, including each one's strong and weak points.

CICC's 24 technical-paper sessions span a wide range of device, circuit, process, methodology, modeling, and EDA topics for analog, digital, and mixed-signal chip design. Among the more interesting sessions are Not Your Father's FPGA: Programmable Systems-on-a-Chip (Monday morning), Broadband Wireline Transceivers (Monday afternoon), Modeling for High Speed Digital Design (Tuesday morning), Modeling for Analog Design (Tuesday afternoon), and Innovations in SOC Applications and Technologies (Wednesday morning). Along with these significant sessions are many individual outstanding papers.

An invited paper by Asad Abidi, Behavioral Modeling of Analog and Mixed Signal ICs, describes case studies of mixed-signal designs using behavioral modeling in place of circuit-level Spice modeling for more efficient design simulation. The three circuits Abidi discusses—high-speed A/D converter, disk-drive read channel, and frequency synthesizer—have simulation requirements that preclude Spice-only simulation. For example, for the 12-bit, 100 MHz A/D converter, the designers used MATLAB for architectural design investigation along with Cadence's SPECTRE as a mixed-signal, mixed-level design environment. Abidi notes that the A/D designers used behavioral modeling not only for circuit blocks, but also for single transistors to correctly model harmonic distortion. In fact, modeling for blocks that operate in the phase domain, such as PLLs and frequency synthesizers, can only be done with behavioral models.

Addressing high-speed serial links is A 2 Gb/s High Speed Link with Differential Simultaneous Bi-Directional I/O, by Cecchi, Hanson, and Preuss. The paper describes uses of differential simultaneous bi-directional switching to double the data bandwidth of an existing 1 Mb/s link by letting a physical channel carry two independent data streams. The authors use pre-compensation to reduce inter-symbol interference, or pattern-dependent jitter, caused by long wire, high-data-rate links. Along with the desired data-rate increase, the authors discuss the need for different ways of testing and verifying a system based on differential simultaneous bi-directional switching.

A very interesting memory technology is described in FeRAM Device and Circuit Technologies Fully Compatible with Advanced CMOS, by Toyoshima et al. The paper describes ferroelectric capacitor RAM (FeRAM) and nonvolatile SRAM technologies. The two-transistor/two-capacitor (2T/2C) FeRAM uses a special stacked-capacitor cell that goes in after multilevel metallization, eliminating the ferroelectric capacitor deterioration that occurs after exposure to certain backend processing steps. The 0.35-micron 2T/2C FeRAM, designed for smart cards, has a wide operating voltage (2.7-5.5V), high read/write endurance of more than 100 billion cycles, and low current consumption (0.3 mA at 2.7V and 2.5 MHz). The 0.25-micron nonvolatile SRAM, also using two ferroelectric capacitors, uses only six transistors. A unique architecture eliminates the need for extra transistors to isolate and discharge the capacitors. At 2.5V, a 512-byte memory has an estimated 6 ns cycle time and dissipates 2 mW at 5 MHz.

Rounding out CICC are the conference's traditional keynote and luncheon speakers. Monday's keynote, given by Lloyd Carney, Nortel Network's Wireless Internet Network Solutions President, will talk about Global Wireless Internet Momentum. The presentation will cover how the Internet is driving, and will continue to drive, communication and commerce through the convergence of the Internet with wireless communications. Mr. Carney will also give Nortel's views on what technologies will lead the next "Internet wave". The always-entertaining conference luncheon, on Tuesday, will feature Michael Workman, IBM's vice president of storage subsystems development. Mr. Workman will blend music and video into a talk on Storage Technology: Trends, Enabling and Enabled Technologies.