Like many of you, I've survived another "DAC Attack" (not to be confused with the "Hack-a-Shaq", taking place at the NBA finals next door). I found this year's Design Automation Conference in Los Angeles to be one of the more interesting DACs in recent years. This year's show featured more new EDA tools and tool suites than in the past few years, many of them quite innovative. A number of themes were evident in both the technical conference and on the show floor, including:

• The explosion of Web-enabled design, encompassing both tools and services
• Key mergers and acquisitions, particularly in the printed-circuit-board (PCB) arena
• Continuing interest in synthesis-to-physical-design timing closure
• The ongoing search for the next great design language beyond Verilog and VHDL
• Increased emphasis on design verification throughout chip and board design cycles
• More attention placed on tool suites addressing major portions of design as opposed to point tools for individual design tasks.

Web-Enabled Design
Companies offering design tools, design services, and software to facilitate design collaboration were in abundance at DAC. Startups with pay-per-use tools (some having free trial periods) included Barcelona, with its Picasso op amp and Dali RF passives optimization design software, and Toolwire, with tools for FPGA and Triscend's configurable system-on-chip (CSoC) designs.

Toolwire's Design Chain Management (DCM) network represents the company's expansion into the design support, technical training, and on-line component information segments of the electronics industry's growing business-to-business (B2B) operations.

Another electronics B2B newcomer, SiliconX, launched its IC design-chain portal, SiliconX.com. Operating as a coordinator, www.SiliconX.com will include third-party design services, silicon intellectual-property (IP) libraries, EDA tools, wafer fabrication, chip packaging, chip assembly, test services, and equipment. The company calls its integration of chip-design information, tools, and services design-chain management, analogous with the supply-chain management products offered by some PCB companies.

Two companies, Sonics and Simutech, demonstrated web-based tools going beyond silicon-IP evaluation and attacking the problem of SOC design. Sonics' Socworks combines a number of B2B partners, including tool suppliers, service providers, and a silicon foundry, with its own SoC design software.

Using a Web browser, you can register on Socworks (www.socworks.com), a free site, to start a design session with a private workspace.

On the site, you have a searchable silicon-IP catalog and a number of pre-configured application platforms, such as ATM, VoIP, printer, and digital camera, that you can use for design exploration. Using Sonic's SOCcreator tool and SiliconBackplane MicroNetwork, you configure a platform with desired silicon cores from the IP catalog to match your specific design requirements.

You then simulate the SoC combination using supplied core or modified stimuli packages available on the site. The simulation gives you a report of system performance and functionality, helping you optimize the SoC design for a specific configuration and core content for the desired application. From that point, you can get a quote from a core vendor or link to VCX, another Socworks member, for assistance in core acquisitions.

Simutech's Web-based SoC evaluation encompasses a new software package, eValab Platform, which complements the company's RAVE prototyping system. The eValab Platform, an updated RAVE system, comprises the eValab Server, iLab Client, and eValab web-ware library. The server supports multiple evaluation sessions on a single server. Each session, an iLab Client supports silicon IP selection, simulation parameters, and results analyses. The library contains a web-control panel and templates for either a preset and parameterized core evaluation (iDatasheet) or an interactive environment (ILab) for a more detailed analysis with a user-defined testbench.

Finally, Sapphire Design Automation is following the example of Cadence, forming internet-based "communities" for two of its products, Pspice simulator and Specctra router. Sapphire's new site, www.noisecorrect.com, supports the company's new NoiseView tool for analyzing data-dependent noise and glitches on a chip. Similar to Cadence's communities, Sapphire's site contains tutorials, services, and software supporting the NoiseView tool and dealing with eliminating on-chip noise in general. You can also access examples, white papers, and a chat room on the noiseview.com site.

PCB Mergers/Acquisitions
Recent mergers between and acquisitions by PCB design-tool vendors have demonstrated the continuing consolidation in this segment of the electronics industry. Following the combination of Summit Design and Viewlogic, the new company, Innoveda, announced its acquisition of PADS Software the week prior to DAC.

Many people had speculated on the "marriage" of Viewlogic and PADS over the past couple of years; rumor finally became reality. With the addition of PADS' BlazeRouter autorouter and HyperLynx signal-integrity (SI) and electromagnetic-compliance (EMC) tools to its existing PCB-design tools, Innoveda will try to give PCB's "Big three"—Mentor Graphics, Cadence, and Zuken, with about one-third of the world PCB design-tool market apiece—a run for their money. It will be interesting to see at next year's DAC whether all four PCB design-tool companies still exist as separate entities.

Using technology from its recent acquisition of Incases, Zuken announced its Board Integrity Solution for high-density PCB and multichip module (MCM) designers. The tool includes SI and EMC screening against pre-defined constraints, an area where Incases' tools excelled. Zuken also has a new tool for designing chip packages, Advanced IC Packaging, for ball-grid-array (BGA) and chip-scale package (CSP) designs. The tool designs capture, package synthesis, routing, and computer-aided manufacturing (CAM), and has links to Ansoft and Agilent tools for RF and SI analysis.

Chip-Design Timing Closure
Companies continue to develop and enhance technology for reducing expensive chip logic-synthesis/place-and-route iterations. Delivering on a promise made earlier this year, Magma Design Automation's Blast Chip IC Implementation System let you take a chip from an RTL representation through final implementation. The tool integrates the company's newly released gain-based synthesis technology with Blast Fusion, Magma's physical-design tool.

Expanding beyond physical design and optimization, Blast Chip encompasses:

• Synthesis
• Logic optimization
• Clock, power and timing estimation
• Extraction
• Place and route
• Signal integrity and congestion management.

Monterey Design Systems enhanced Dolphin, the company's physical-design system. Dolphin 1.2 is designed for technologies at 0.18 microns and below. The new Dolphin can calculate path delays induced by crosstalk interactions on interconnects that are in close proximity on a chip.

Other improvements to Dolphin include:

• Advanced manufacturing rules in Dolphin's global optimization function
• New timing analysis that analyzes multiple aggressors for best- and worst-case SI analysis
• Better clock-tree synthesis
• Enhanced logic optimization.

Supplementing its First Encounter chip physical-design and optimization tool, Silicon Perspective recently announced its Hierarchical First Encounter (HFE) Design System. HFE can be used for block optimization and assembly at the top-level of your SoC designs.

The tool's two primary components are Partition Optimizer, which partitions the design to optimize the efficiency of back-end design tools, and Hierarchical-Interconnect Synthesis, which produces the final top-level interconnect between the hierarchical blocks. The synthesis module includes a top-level router, top-level optimization, and clock-tree routing. HFE requires Silicon Perspective's First Encounter, which provides the physical engines needed by HFE.

High-Level Design Languages
Many companies at DAC touted new products and relationships to assist chip designers at the conceptualization and partitioning stages of their designs. Over the past year, tool vendors and design houses have introduced a variety of open and proprietary languages to work above Verilog and VHDL. At this time, it appears that C/C++ has the upper hand.

Frontier Design added SystemC capability to its A/RT Designer tool, which lets you do system architectural exploration based on C algorithms. With the enhancement, the A/RT Designer can accept SystemC fixed-point designs along with ANSI C algorithms and generate optimized hardware using datapaths, multipliers, adders, memories, and other functional hardware blocks.

In another endorsement of C/C++ design, IMEC demonstrated a hardware implementation of a standalone-networked camera that the company developed in less than six months using a C++ design environment called OCAPI-xl.

Other related products at DAC included CynApps' integration of Cadence's TestBuilder technology with the CynApps Cynlib class library, and CoWare's enhancements to SystemC 1.1 to better represent communication interfaces and to improve system-level events handling.

TestBuilder, a C++ based testbench library within the Cadence Verification Cockpit, lets users develop hardware testbenches. Cynlib is a C++ class library, facilitating hardware description directly in C++. With TestBuilder and Cynlib, you can design and verify the design in C++. You can then synthesize the design's HDL representation using CynApps' Cynthesizer for RTL synthesis by standard design tools.

CoWare's abstract communications capability allows you to completely specify an interface, without specifying how it is implemented using channels that independently define the direction of data and control. You can also associate a high-level protocol with the channel. The company's Remote Procedure Call capabilities improve SystemC's ability to handle system-level events and work above the event-driven and cycle-based operations of HDL simulators.

Design Verification
Denser and small chips mean more difficult design verification, for both hardware and embedded software. At DAC, verification hardware and software vendors showed some products and services that functioned in a traditional environment and some that used the Internet to enhance their availability and functionality.

Aptix launched their www.eSOCverify.com site, a web-based service to configure SoC designs for emulation. Customers put their designs in a secure location and Aptix provides the software and engineering support to emulate and verify the design.

Quickturn has two new SoC verification products, Mercury^Plus and Rapid Prototyping System (RPS). Based on a new, custom FPGA optimized for emulation, Mercury^Plus improves upon its predecessor, Mercury, with faster compile times, higher capacity, better debug productivity, and more accurate circuit modeling. RPS complements Quickturn's in-circuit emulation systems with a lower cost modular approach. This configuration lets you build system prototypes from silicon-core building blocks.

A newcomer, Tharas Systems, entered the hardware accelerator market with its Hammer 50/32 product. The accelerator uses ASICs in a memory-mapped architecture, rather than traditional FPGAs, to speed up RTL simulation from 10,000 to 100,000 cycles/sec. Hammer's software includes a compiler with HDL analyzer, domain partitioner, scheduler, targeter, runtime manager, and debugger.

0-In Design Automation has shipped 0-In Search, its EDA tool that uses semiformal verification technology to find corner-case bugs in complex SoCs. 0-In Search works with the company's 0-In Check design-instrumentation tool and CheckerWare verification library. The product combination provides a white-box verification system that uses knowledge of a design's internal structure to provide more efficient and thorough functional verification.

Joining the other major EDA vendors (Avant!, Cadence, and Synopsys) with formal verification tools, Mentor Graphics introduced its FormalPro equivalence checker. FormalPro is targeted at complex, multi-million-gate SoC designs. The tool offers high-capacity verification, an advanced debug environment, and automation to streamline complex SoC verification.

Tool Suites
Over the past 15 years or so, the EDA industry has alternated its emphasis on integrated tool suites with best-of-class point tools that dovetail into an existing design flow. Integrated suites are, on the surface, very attractive since they have the potential of having single-vendor support, a common GUI, common data base, and because take less time to master.

A tool suite assumes that the suite vendor has an impossibly wide range of expertise and, therefore, is only as good as the weakest tool in the design chain. Conversely, a point tool can come from a company whose expertise is focused on the problem the tool addresses. This could make the tool, again potentially, the best at doing the job for which the company developed the tool.

However, point tools depend on good operability with the tool suites in which a designer places the tools. While standards have definitely improved and become more widespread over the past couple of years, designers still face significant barriers in "seamlessly" using a third-party point tool in an established tool flow.

At DAC'2000, integrated tool suites definitely garnered the most attention. Along with performance and ease-of-use, tool vendors lauded their ability to handle increasingly larger portions of a chip or PCB design flow. Companies achieve this enhanced integration in three ways:

• Improved internal tool development
• Technology relationships with other tool vendors, along with system developers and design houses
• Company mergers and acquisitions.

Enhanced integration puts the onus on point-tool vendors to develop products that "go with the (design) flow".

But Wait, There Was More
DAC exhibitors showcased many other products that fit outside my "theme" areas. The following examples summarize some of the most noteworthy.

• Circuit Semantics DynaModel
  You use this tool to characterize hard silicon intellectual-property (SIP) blocks. This capability is valuable when removing legacy cores such as those you migrate to a new process technology. DynaModel generates fully functional Verilog simulation models abstracted from hard IP, so you can integrate the blocks into a HDL-based chip-design flow. A further benefit is that the functional Verilog models simulate much faster than circuit-level models, such as those in Spice.
  
  
• Chameleon Systems CS2000
  Using the company's proprietary eConfigurable technology, Chameleon's CS2000 family of communications processors provides a high-performance reconfigurable platform. According to Chameleon, the CS2000, implemented in 0.25-micron technology, delivers 24,000 16-bit MOPS (million operations-per-second), 3,000 16-bit MMACS (million multiply-accumulates-per-second), and 50 channels of cdma2000 chip-rate processing.
  
  
• Cadence Virtuoso Custom Designer
  A connectivity-driven, full-custom chip-design suite, Viruoso encompasses automatic device generation, placement, interactive and automatic routing, layout-versus-schematic (LVS) checking, design-rule checking (DRC), and optical-proximity (OPC) /phase-shift mask (PSM) analysis into a single product.
  
  
• Co-Design Automation SYSTEMSIM
  The SYSTEMSIM simulator provides, according to Co-Design, orders-of-magnitude performance improvements while solving SoC verification issues. SYSTEMSIM provides mixed simulation of Verilog, C/C++, SystemC, and SUPERLOG. The company's SYSTEMEX, a tool to transform abstract system descriptions to HDL code, complements SYSTEMSIM.