Design Article
Power Integrity Analysis for Billion Transistor Full-Custom Designs
Yaron Kretchmer, Altera, Li-Pen Yuan, Shekhar Kapoor, Synopsys
9/17/2006 5:53 PM EDT
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits. One of the key challenges that has emerged is the need to optimize the power distribution network so that problems associated with voltage drop and electromigration (EM) can be avoided. Power integrity is a critical problem at 90nm and 65nm process nodes for ASIC, FPGA, full-chip custom designers and other designers alike.
As engineers tackle complex, larger designs (such as full-custom), there is a need for innovative approaches to power integrity analysis that enable results to be achieved quickly with reasonable computing resources, but without compromising accuracy.
This article outlines typical power integrity issues in today's advanced designs and highlights the unique challenges of full-custom designs. The features of different power modeling techniques are described, and ways to mitigate the primary issues are considered using custom design specific modifications. The key objective is to enable fast yet accurate analysis. Some results from the analysis of a real world billion-transistor full-custom design are presented to substantiate the proposed power integrity methodology.
Power Rail Problems
Voltage drop refers to the decrease in voltage that is due to Ohm's Law operating on the current and resistance through the power network. Voltage drop occurs through the package pins, bond wires and pads, as well as through the metal layers on the die itself. While the supply voltage may meet the specified requirements at the package pins, judicious planning and design of the power grid on the chip must ensure that the power specification is met across the entire chip.
As process geometries have shrunk, so too have the required supply voltages, but the frequencies have gone up, resulting in decreasing margins available to accommodate voltage-drop (Figure 1). If voltage drop is not limited, the consequences can be disastrous. If the voltage drop increases beyond the target threshold, the operating performance of the cell is reduced. Voltage drop also affects noise immunity, and under extreme conditions, leads to functional failure.
Electromigration is another critical issue that is more prevalent as feature sizes decrease. EM is caused by high current densities causing metal migration, resulting in open or short circuits. EM also causes performance and reliability degradation over time.
Implementation of an advanced FPGA product roadmap is based on a successful transition from 90nm and 65nm semiconductor processes that supports a very high level of integration. Robust power integrity planning, as a platform for addressing the problems associated with voltage drop and EM, is critical to enabling a full-custom product development roadmap.
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