Escalating the issues " power

Consider a 90nm chip that requires the use of multiple supply voltages and power shut-off capability to reduce its operational and standby current levels, which will increase battery life, which in turn improves end product value. Ideally, minimizing power in an optimal fashion will push the entire design to a timing critical stage (any non-timing critical region, it can be argued, is wasting energy). Design teams that use over constraining as the method of managing the downstream physical effects of wires are thus wasting energy and detracting from the end product value. Instead of a blanket approach, such as over constraining the entire design, design teams must increase the accuracy of their physical modeling. Thus, designing with power and design with physical effects are intimately interwoven.
Having multiple power domains that can power down represents new and unique challenges to functional validation and test. Waiting to validate and verify the functional implications of the power control structures in a design is a risky proposition. By the time a full transistor netlist is available, the project clock has ticked down to crunch time. Design teams must adopt methods to model and validate power intent, which further complicates an already acutely critical issue. In the same vane, the design for test strategies needed for highly timing critical designs that employ advanced low power techniques adds new dimensions to the complexity of designing with test, which also impacts physical design, timing closure, and power (Figures 1 and 2).

Architecting a solution

RTL designers provide the fountain from which successful chip projects flow. Conversely they can also sow the bad seeds of programs fraught with problems, delays and failures. In other words, how a project starts is pretty instrumental in its ultimate success or failure. Minimizing risks faced by logic design teams means upgrading the front-end flow from the evolutionary set of technologies of the industry's current front-end offerings. A new approach to solving growing challenges is needed, addressing flow bottlenecks and inefficiencies in standard production flow (Figure 3). The right solution for RTL design teams can address these challenges and reduce overall risks with:

• "Design with Power"—power-aware design, verification, and implementation flows are now a must to remain competitive in the evolving global market.
• "Design with Verification"—delivering on the promise of early verification by design teams to shorten the overall time to market, while significantly raising design functional quality.
• "Design with Physical"—reducing the logic-physical late iterations by elevating the level of abstraction to design teams.
• "Design with Test"—accelerating development of high quality test infrastructure and enables design team to minimize cost of test.
• "Design Logical Signoff"—helping with a backend handoff checkpoints for design teams to achieve front-end signoff closure quickly and accurately, improving quality.
• "Design Management"—providing a plan and metrics-driven flow across the entire design and verification tool set, and bringing unparalleled predictability from plan to closure.

Because of the ever increasing intertwining of the power, verification, test, and physical modeling design issues, the challenge for the design team is to bring all of these elements to bear on the whole design problem. A holistic approach is critical to achieving a successful outcome. While all of these issues are virtually inseparable, some further background on each should help to catalyze a clear path to action.
Design with power
Design with power

Design with power is needed as power has become a ubiquitous design issue, nearly independent of end IC target market. At 90nm and below, a majority of design teams are using at least one new design technique to mitigate power dissipation. There are a number of known techniques for reducing power consumption; in the past, their implementation has been labor intensive, risky, and for the most part, relegated to the back-end of the design process. Current solutions for low-power design enable design, verification, and implementation of advanced low-power design techniques using a full solution approach that reduces the effort and risk associated with the application of multi-supply voltage and power shut-off design techniques. Each advanced power lowering technique today requires tool specific directives to implement, making the design flow manual, tedious to implement, and highly error prone.

Fortunately, a new Common Power Format (CPF) has been developed and is being refined by participants in the Power Forward Initiative. CPF holistically captures the designers' power intent in a single file so that it can be applied consistently across all steps and tools in the design flow including design, verification and implementation. The complete power intent captured in the single CPF file facilitates automation of power lowering techniques, making low-power design easier.

Design with verification

Design with verification is needed as it is no secret that functional errors are the main source of silicon re-spins. As Moore's Law marches forward, functional verification complexity follows its own exponential growth path. Effective early functional verification starting with design team formal analysis, followed by simulation and then hardware-based techniques, with coverage-driven verification management, directly impacts design team productivity and quality and reducing time-to-market. Organizing verification requires planning, that can automatically correlate coverage results with the intended test no matter which technology is used for verification.

Design with physical

Design with physical is needed as physical modeling issues have been challenging design teams since the transition from .25-micron to .18-micron technology. The problems have been exacerbated with the introduction of each new process node. The handicaps of the incumbent solutions have led design teams down two principal roads: either ignore interconnect all together (e.g., use zero wire load models), or take responsibility for some of the aspects of physical design themselves (e.g., hand-off post physical synthesis placed gates). Both of these approaches merely skirted the issue of better interconnect modeling in the front-end design process. The new solution directly improves the interconnect modeling, leading to fewer iterations and better designs.

Design with test

Design with test remains an important aspect of correct design implementation, with the design for test consideration being crucial up-front in the design process instead of proceeding with an error-prone post-netlist process. The ability to accelerate the development of the high quality test infrastructure enables design team to minimize cost of test.

Design logic signoff

Design logic signoff is another must-have for effective design process, enabling design teams to provide a clean front-end handoff to the back-end process. Leveraging syntactic and semantic-level checking, structural diagnostics, equivalence checking, timing constraint validation, and static timing analysis checkpoints helps design teams achieve front-end signoff closure quickly and accurately, improving overall quality.

Design Management

Design management costs are projected to continue to skyrocket if new methods that provide visibility and predictability to the design process are not adopted. Design Management is a must as the plethora of technologies used by design teams, along with tool interdependencies, results in an ad-hoc unpredictable process where it is hard to plan and track execution progress. By extending the verification management capabilities onto design, up-front design implementation planning with both design and verification metrics and milestone-based tracking provides a high degree of predictability, highlighting critical paths and helping project managers reduce the risks associated with complex ASIC and SOC design, and enabling a complete flow management process from plan to closure (Figure 4).

Conclusion

A set of targeted solutions for logic design teams aiming at reducing the overall risks associated with front-end design and verification while improving productivity, quality, and predictability is a new success requirement for logic design teams. Mounting data volume supports the critical need to take action if the predictability crisis is to be averted. Those teams that do make the tough decisions for change will be rewarded with capabilities to make more competitive designs, with a critical advantage in design process predictability.
The incumbent solutions that have been slowly evolving, in a process akin to a combination mutation and decay do not have the capacity to support new "design with" methodologies. While the four forces of change, power, verification, test, and physical effects, have demanding attention and forcing the old methods into obsolescence, new solution architectures that were made to "design with" will be aggressively deployed by all of those logic design teams that want to create a competitive advantage.

About the Authors

Dr. Chi-Ping Hsu is Corporate Vice President, R & D and Chief Strategist for Products and Technology at Cadence. He holds a Ph.D. degree in EECS from University of California, Berkeley, and BSEE degree from National Taiwan University.
Andy Eliopoulos is vice president, R&D, at Cadence. He is responsible for the Incisive simulation products. He holds a BSEE from the University of Akron.