Using Fill Synthesis for Enhanced Planarization

Introduction

In the past decade, chemical-mechanical polishing (CMP) has emerged as the predominant planarization technique for shallow trench isolation (STI) and back end of the line (BEOL) metallization. To produce planar wafer surfaces, CMP relies on two mechanisms: (1) the chemical reaction between slurry species and the wafer surface, and (2) mechanical abrasion between a pad and the wafer surface. CMP consumables (pads and slurries) have improved significantly over the years; however, the smoothness of the surface is still not perfect and significant post-CMP surface topography variations can occur for some layout patterns. Failure to meet the surface topography variation constraints leads to degradation of transistor characteristics in the case of STI, and electrical shorts or increased wire resistance in the case of BEOL interconnects, all of which are detrimental to circuit yield.

One design for manufacturability (DFM) technique that improves surface planarity in today's advanced technologies is the insertion of non-functional patterns, i.e., fills, dummies or waffles, into the design layout so that the density distribution within a die is as uniform as possible. This process is called "fill synthesis" or "dummy insertion" or "waffling". It is governed by the CMP design rules (DRs), which specify the allowed density upper and lower bounds, sizes of dummies, dummy-to-dummy spacing, and spacing between dummies and functional trenches or wires based on the planarity requirements for the inter-layer dielectric (ILD) overlying the metal. Fill synthesis is normally implemented by a physical verification tool, which finds unoccupied areas and inserts the prescribed dummies that satisfy CMP DRs into those areas. The insertion can be done in multiple passes, each with varying dummy sizes, so as to optimize the amount and location of inserted fills.

This tutorial describes some of the different fill techniques that may be used to enhance planarization by reducing the variation of metal densities in different regions of the chip. Chip designers may find this information instructional in helping understand the fill insertion process so that they can make informed decisions about which techniques will achieve the desired planarization goals while preserving the power and timing integrity of their designs.

Fill Synthesis Requirements

Process design rules contain requirements for pattern density on each layer. These rules are expressed as minimum and maximum percentages within specified "window" sizes. For example, the minimum and maximum densities for Metal-1 might be 20% and 80%, respectively, within any 100 x 100 micron window. Such a density rule is verified in a discrete set of windows that are "stepped" in overlapping fashion across the die, as illustrated in Figure 1. The figure shows the step size as a fraction of the window size, i.e., w = 100um and r = 4. Verification of density constraints in a discrete set of windows helps limit the computational complexity of the fill synthesis and verification tasks, but smaller values of r can lead to greater error with respect to a "continuous" verification.

In our discussion, we classify the various fill techniques into two fundamental approaches: purely geometric, versus electrically aware. We also explore some advanced techniques that incorporate aspects of both approaches.