Mathematical package helps in circuit design

Lumped Gate ESR Model

Lumped parameters models offer insight into the phenomenon and offer engineers a range of tools from the simple Ref. [1] to the more complex Ref. [2] to evaluate the susceptibility of a given synchronous rectifier for cross conduction in a synchronous buck converter.

In order to derive the node equations to be solved for the shoot through voltages in this case, we must use a complete lumped circuit for a synchronous rectifier including inter-electrode capacitances, resistances and source and gate inductances.

Figure 2 shows the results of the solution as can be seen annotated. The simple model results in the lowest value of gate-source voltage during shoot through. The more complicated model adds both the parasitic gate and source inductances and clearly results in higher shoot through voltage.

Finally adding the inter-electrode resistors results in the largest shoot through voltage. It is worthwhile mentioning that the gate-source voltage internal to the die is different from that between the external gate and source terminals on the device. Also the peak value is larger and takes place at a different time leading to the conclusion that simple external observations are not sufficient to determine whether cross conduction takes place or not when measured in the lab.
Figure 3 shows the current flowing in gate-drain capacitance, Cgd, and to a large extent in the gate driver for a drain-source rise time of 1ns. This large current, 16 Ampere, will add to the drain current of the control MOSFET and aggravate the dynamic losses situation.

Distributed Parameter Model

In reality all the MOSFET parameters are distributed over the entire surface of the silicon device that leads to a very interesting situation. This situation is namely one in which the equations that govern every cell on the device are different from any other cell and hence, cross conduction will take place, when it does, at different times and at a varying magnitudes.

Figure 4 depicts the complete model of a synchronous rectifier (between dotted lines) used in the analysis with distributed gate resistance, Rg, gate-source capacitance, Cgs Cgd and. The equivalent circuit used in the mathematical analysis using MapleTM was done by dividing the die into ten segments (S1...S10) with the assumption that each cell within a given segment has identical conditions of voltages and currents to each other cell. MOSFET segments S1...S10 represent the synchronous rectifier if it were sliced in ten smaller sections with proportionately scaled parameters. This will simplify the solution and help us get an idea about the distribution of shoot through current and losses in each of the segments.
Using the above assumption, Figure 4 depicts the circuit used for the derivations of the voltages and currents equations transform for the distributed parameter case. We assume that the ten segments where cells in each segment has identical conditions. A set of eleven simultaneous differential equations were derived and solved using Maple. The resulting equations are too extensive and long to be displayed here. Figures 5 through 7 show the results in a 3 dimensional format that is easy to visualize and understand.

Assuming a step voltage at the drain of the MOSFET, Figure 5 shows the gate-source voltage of one segment of the synchronous rectifier, the gate threshold voltage plane and the drain current as a function of time and Cgd. The current starts conducting after the gate-source voltage level crosses the gate threshold voltage and spikes rapidly as the voltage increases.
Very small differences in the gate-to-source voltage results in significant differences in drain currents. These results clearly show that segment currents are not identical from one segment to the other and segments farthest away from the gate pad conduct the majority of the drain current while the drain current in the remaining segments represents a very small percent of the total device drain current. This leads to the conclusion that a small percentage of the die surface takes the majority of the shoot through power losses while the rest of the die may or may not have any shoot through whatsoever.

If the part of the die that is taking the majority of the power dissipation can withstand its thermal effects without overheating beyond 150°C " 175°C under the worst case conditions, then there is no harm done. As the rise time increases to achieve lower dynamic power dissipation, the cross conduction problem is likely to get worse unless the MOSFETs are designed in some innovative way to eliminate shoot through altogether and only then, cross conduction could no more poise a challenge to the design engineer.

Figure 6 depicts the drain current and shoot through voltage of segment number10 as a function of the gate-source capacitance Cgs. Notice that among all the parameters considered, changes in Cgs has the largest influence on the on the drain current and consequently the shoot through losses.

Figure 7 shows the effects of the gate ESR, Rg, on the drain current and the shoot through voltage.
One may observe that while the influence of both Cgd and Cgs is limited in a very narrow window of typical values the effect of Rg is wide reaching along the entire range considered.

Conclusion
The use of the mathematical software package Maple^TM allowed us to investigate the interaction of all the important parameter in a three dimensional representation, 3D, that helps understand the extent of the interdependencies. 3D graphing offers a very powerful visualisation tool of the complete results. To achieve the same results using any numerical simulation environment requires enormous amount of batch simulation, data compiling and graphing

References:
(1) Evaluating MOSFET Susceptibility for Cross-Conduction, Alan Elbanhawy, Fairchild Semiconductor, PCIM Magazine, Europe
(2) Shoot through analysis with parasitic inductance, Alan Elbanhawy, Fairchild Semiconductor, PCIM Europe Conference 2004

About the Author:
Alan Elbanhawy is Director, Computing and Telecommunication Segments Advanced Power Systems Center at Fairchild Semiconductor. He holds a B.S. in Electrical Engineering. He can be reached at Alan.Elbanhawy@fairchildsemi.com