Analog and Mixed-Signal Connectivity IP at 65nm and below

• Shallow trench isolation (STI) is a fabrication method used to isolate active areas and can cause currents to be different from simulation. It depends on transistor location.
• NBTI degrades PMOS devices progressively over time by an increase in the threshold voltage and reduction in mobility due to negative gate bias and/or higher temperatures, usually around 100+C. The net effect is that the PMOS current drive is degraded over time. This can induce timing failures in digital circuits modeled as a Vsub>th shift.
• Matched devices, like current mirrors and differential pairs, which are asymmetrically stressed, will have an additional mismatch component, in addition to mismatch from processing variations, causing additional system performance degradation.
• HCI degrades the performance of NMOS devices in a similar way, but through a different physical mechanism to NBTI. Unlike NBTI, HCI is a function of the electric field across the channel (i.e. from drain to source) whereas NBTI degradation is a function of the field across the oxide modeled as an Idsat shift.

These effects do have a serious impact on the design of the analog/mixed-signal portions of the connectivity IP and the vendor must have deep expertise in understanding these effects and including them as automated simulation tools.

With these higher voltages, electro-migration checks for potential short conditions must be made. This can occur on dense arrays of conducting thin-film metallic conductors, and over time, high current densities cause these conductors to fail resulting in metal separation. Also, there should be checks for adequate metal widths and checks for metal/MOS/POLY/VIA/ contacts. Therefore, it is important to have an EDA flow that includes automated checks for junction stress, as well as HCI/NBTI degradation simulations.
Circuit layout must also be able to accommodate well proximity effects. Advanced extraction decks include STI/nwell proximity effects, however, these are only back-annotated after layout is complete. Layout immune methodology helps bridge the gap between schematic simulations and extracted simulation results.

Time-Dependent Variations
A good example of time-dependent variations is the impact of NBTI on the input devices of a USB PHY.
In USB designs, for example, the stress on the input devices varies drastically between standby mode and normal high-speed operation. Furthermore, many of these circuits are typically designed with PMOS input stages in order to handle the low common mode voltage in high-speed operating mode. As a result, these circuits are very susceptible to NBTI induced degradation (V_th shifts) which can ultimately compromise their compliance/functionality by causing large input offset voltages on these circuits. An application of temporal NBTI effect can be seen in modern USB designs. The differential USB data lines (DP/DM) are held at opposite polarities during suspend mode, i.e., 3.3 V and ground.

The stress on the input devices varies drastically between suspend mode and normal operation. The duty-cycle between suspend and normal operation can vary, but one could assume 50 percent for sake of an example. Typically, there is sensitive input circuitry connected to the differential data lines (DP/DM), for example, squelch detector, high speed receiver, disconnect detector, etc. Furthermore, many of these circuits are typically designed with PMOS input stages in order to handle the low common mode voltage in high-speed operating mode. As a result, these circuits are very susceptible to NBTI induced degradation (Vt shifts) which can ultimately compromise USB compliance/functionality by causing large input offset voltages on these circuits.

Fortunately, scenarios like this are well understood, and so in this particular case, the designs are usually modified to block the large delta Vgs across the sensitive input circuitry when suspended. The true benefit of NBTI modeling/simulation tools are in uncovering non-obvious/subtle scenarios and circuits where designers may not have recognized the potential for large Vt shifts in their design. These tools will enable designers to uncover long-term shifts in the design due to NBTI stress early on in the design process, thereby enabling circuit modifications to mitigate the impact and improve system reliability and performance.