Design Article
Topology Planning and Routing
Dean Wiltshire, Mentor Graphics Corporation
7/30/2007 8:56 AM EDT
Topology Work Flow
In Figure 1, we see the role of the design engineer capturing IP by placing the few necessary components and planning critical interconnect flow between these components. Once captured this information is seamlessly provided to the PCB designer where they can complete the remaining design.
1. Flow of PCB design with design engineer capturing IP and seamless integration with PCB designer to finish design.
Rather than going through the interactive and iterative process between engineer and designer to capture the correct intent, the design engineer has captured this information and done so accurately making it useful to the PCB designer.
For so many designs, the engineer and designer go through an interactive placement and routing, consuming both professional's valuable time. Historically, it is a necessary interaction, yet with time consuming inefficiencies. The original plan provided by the engineer may have been a hand sketch without appropriate scales of components, bus widths or pin outs.
As the designer engages with the design, placement of certain components and interconnect are captured by the engineer using topology planning techniques. Yet, the design is not complete with other components to place and probably other IO and bus structures to capture and all interconnects complete.
Like the design engineer, the PCB designer employs topology planning while interacting with both placed and unplaced components. Working this scenario produces the optimum placement and interconnect plan " providing density efficiencies.
As critical and dense areas are placed and topology plans captured, placement may be completed prior to the finished topology plan. Therefore, some topology paths may have to work with existing placement " they're a lower priority, yet still need to be connected.
Detailed Topology Planning
So a portion of planning occurs around placed components. Further, this level of planning may require greater detail to provide the necessary priority for other signals. The example shown in Figure 2 is of detailed planning after components are placed. There are seventeen bits to plan for this bus and they have a fairly organized flow.
2. These Bus' net lines are the outcome of higher priority topology planning and placement. So, a topology plan will be created to address this bus without manipulation of component placement.
To plan this bus, the PCB designer considers the existing obstacle, layer rules and other important constraints. With these inputs they plan the following topology path for this path as shown in Figure 3.
3. The bus is now planned.
In Figure 3, detail "1" has planned for the component pins on the top layer "red" to escape the component pins and join a topology path at detail "2". This is done with an unpacked area with only layer 1 identified as a routing option. This may seem obvious at this point of the design and the routing algorithm would use the top layer to connect to the red topology path. However, obstacles might provide other layer options to the algorithm before auto-routing this particular bus.
As the traces get organized into a packed path on layer 1, the designer then plans a transition at detail "3" to layer 3, to take the bus the distance throughout the PCB. Note, this topology path on layer 3 is wider then the top layer – the path is considering the additional space needs to accommodate impedance. Further, the design has also specified the exact location for layer transitions – or 17 vias.
As the topology path drops through mid right section of figure 3 at detail "4", many single bit T junctions are needed to escape from the topology path of connections to individual component pins. The designer's preference is to keep most of the connection flow on the layer 3 and breakout to other layers for connection to component pins. Therefore, they draw a topology area indicating connections from the main bundle to layer 4 (pink) to make these single bit T junctions to layer 2 and then use another via to connect to the device pins.
The topology path continues on layer 3 to detail "5" to connect to the active device. These connections then go from the active pins to pull-down resistors below the active device. The designer uses another topology area to specify connections from layer 3 to layer 1, where the component pins reside for both the active device and pulldown resistors.
This level of detailed planning only takes about 30 seconds to complete. Once this plan is captured, the designer may want to immediately route or create further topology planning and then auto-route all the topology plan. The auto-route results, following the plan takes less than ten seconds. Yet this speed doesn't matter and in fact is wasted time if the intent of the designer is ignored and auto-route quality is poor. The next figures show the auto-route results.
PCB Routing
Topology Routing
4. Results of topology routing with details 1 - 3 explained below.
From the upper left, all connections from the component pins follow the designer's expressed intent and stay on layer 1, compressing into a packed bus structure as shown in Figure 4, detail "1" and "2". At detail "3" the transition between layer 1 and 3 occur, employing a space efficient via pattern. Again, impedence concerns are covered with wider traces and greater clearances as represented by true width paths.
5. Results of topology routing with detail 4 explained below.
In Figure 5 and shown with detail "4", the topology path swells where vias are needed to accommodate single bit T-junctions. Again, the plan was followed with these single bit T-junctions respecting the designer's intent, routing from layer 3, to layer 4. Further, the traces on layer 3 stay as packed as possible swell around the inserted vias, but quickly compressing again.
Figure 6 shows the auto-routing results at detail "5". The active device connections from layer 3 require a transition to layer 1. Here the vias line up above the component pins and the layer 1 traces connect to the active device then on to the pull-down resistors on layer 1.
6. Results of topology routing with detail 5 explained below.
To summarize this example, the 17 bits are planned in detailed to four different device types, representing the designer's intent of layers and path flow, captured in about 30 seconds and followed with high-quality auto-route results, provided in an additional ten seconds.
By raising the level of abstraction from traces to topology planning, the overall interconnect time is drastically reduced and before the interconnect is started there is a real clear understanding of densities and potential for completing a design. With knowledge " why keep the traces at this point on the design? Why not continue planning and add traces later, when a complete topology is planned? If the previous example is considered, the abstraction of a plan allows working with one plan instead of 17 individual nets with many trace segments and vias per net. This concept is extremely important when considering the ever present Engineering Change Orders (ECOs).
Engineering Change Orders
ECOs
In this next example the pin outs of an FPGA are not finalized. The design engineer has communicated this fact to designer but because of schedule concerns, they need to advance the design as far as possible before the FPGA pin outs are finalized.
Working with the known pinouts, the designer starts space planning to the FPGA, all while concerning themselves with escaping from other devises to the FPGA as the designer completes the planning. Originally, the IO was planned to be located on the right side of the FPGA but instead is now located on the left. This has caused the pinouts to be completely different than originally planned. Yet, working at a higher level of abstraction, the designer has removed the overhead of moving all the traces around the FGPA to accommodate these changes. Instead, the topology paths are modified.
However, it is not just the FPGA that's affected; these new pin-outs also affect the escape from the related device. To accommodate the flat pack escape into the path, the end of the path was also moved; otherwise a twist of traces would be caused, wasting valuable space on a dense PCB. A twist of these bits would require additional room for traces and vias, yet may not be addressed in the final phases of the design. If the schedule is tight, this may be too much work to make these adjustments to all traces. The point being, by working at the higher level of abstraction offered through topology planning, it is far easier to accommodate the ever present ECOs.
An auto-routing algorithm designed to follow the designer's intent will prioritize quality results over quantity. If a quality issue is determined, it is better the fail a connection than create poor quality routing results. This is true for two reasons. The first being it is easier to connect a failure rather than clean up auto-route manipulations of this and other traces with poor results. And second, the designer's intent is followed and the designer allowed decide quality of connection. However, these points are only useful if connecting the failed traces are fairly simple and localized.
A good example is when the router fails to connect 100% of the plan. Rather than sacrifice quality, a bit of the plan may fail, leaving a disconnected trace. All traces are routed through the plan, just not all the way to the component pin. This ensures that room is reserved for the failed connection and provides a connection that's fairly easy to connect.
Conclusion
Topology planning is a tool that fits into a design flow for PCB's with digital signals. The tool is light weight for the adoption by design engineers but it also allows for specific space, layer and connection flow consideration for complex planning. The tool can be used by a designer either at the beginning of the design or after the engineer as captured their Intellectual Property (IP). It's up to the organization to adopt this flexible tool to best suite their design environment.
Topology router simply follows the plan or intent of the designer by following the plan to provide high-quality route results. When it comes to ECO's, topology planning is far quicker to manipulate than individual connections, providing a faster adoption of the ECO with Topology Router providing fast, accurate results.
About the Author:
Dean Wiltshire is a Product Architect, in the System Design Division of Mentor Graphics Corporation.
