Accelerating Functional Verification

SoC design isn't getting any easier. Escalating IC densities, rising design complexity and increasingly intricate software interactions are conspiring to reduce predictability and drive up cycle-time risk. At the same time the growing use of software-enabled customizations is quickly rendering existing methodologies obsolete. Relentless demand to reduce power, particularly in portable consumer applications, has reshuffled priorities within the design flow. Complicating these trends, few teams have the design experience in-house to handle and manage these rapid changes.

In some areas of SoC design, the EDA industry has achieved major advances over the past few years. For designers developing digital circuits, for instance, automated routing has greatly simplified the manual layout process. The challenges are a little bit more daunting, however, for engineers tackling analog/mixed-signal design or functional verification. Cross domain verification is often ineffective and requires manual intervention. And the escalating data sets and long simulation runtimes that accompany more complex SoC designs complicate modeling, extraction and re-simulation of parasitics and threaten design predictability.

The most imposing obstacle to better designer productivity and improved SoC predictability lies in functional verification. Studies clearly indicate that verification is the single most time-consuming task in any design flow. Many new tools and technologies introduced over the last few years have promised to address these rising verification challenges. But understanding and applying them often undermines team productivity. Few engineers, for instance, have the time to read a 2,000-page methodology manual or explore through repeated trial and error how to get up to speed on a new tool. So the real challenge for many design teams today is moving beyond the traditional tool silo approach where engineers learn about a single tool at one time, and reaching a point where they can easily collect information from multiple tools in a comprehensive way that enables a coverage-driven verification process.

Faster verification
In an attempt to demystify the latest EDA technologies and methodologies and accelerate designer productivity, Cadence has developed a new concept called interactive methodology. This new approach, encapsulated in a functional verification kit, places pages of documentation, a proven methodology, sample verification plans, design and verification IP, tool features and design integration capabilities into a single, menu-driven GUI-based environment. Within this environment, the user can easily navigate and focus on the specific tools or technologies needed without having to read through pages of irrelevant documentation. A designer can start in the middle, the end or the beginning and navigate to any spot in the environment without proceeding in any fixed order. He or she can view an entire verification flow, based on Cadence's Incisive plan to closure methodology, or drill down into specific functions or sub-flows. When the user needs to create a verification plan, the environment will illustrate a flow diagram of the necessary steps. By clicking on an individual step, the user can see a template for each function with accompanying documentation explaining how to perform each task. And by simply cutting and pasting, the engineer can build his or her own verification plan.

This methodology can also be linked to the latest tools, which can be automatically initiated to run a verification session. Engineers no longer have to worry about which tool version is compatible with which design to just try out a new capability. They no longer have to worry about how to get a design to work in several different modes or several different languages. Moreover, the methodology runs on a pre-assembled, fully-functional, real-world representative design so the user can judge upfront how a particular design challenge is addressed in a realistic setting.

Having a comprehensive pre-assembled and pre-built environment that allows the engineer to explore advanced verification techniques offers tremendous productivity benefits. Within this environment users can see simple demonstrations of key SoC verification techniques such as hardware-software co-verification or low-power design. If they have more time available, they can dig down into more detail to see exactly what is required at the code level. By following a well-known and proven methodology, the environment can scale from block through chip level and enable verification component reuse throughout the process. This allows users to not only create context-specific information, but ensure that it is aligned with established flows and use models. In this environment an architect who is testing an idea for a new block can easily understand how to create a transaction-level model, co-verify it in software and ensure it functions within the context of the overall methodology.

One of the key benefits of an interactive methodology is its ability to bring together the efforts of both design and verification engineers. Both groups typically have very different needs and use different metrics. Yet one of the key ways to ensure a project's success is getting both teams on the same page and using a consistent methodology. Designers typically take a hardware approach and need to know how to apply a test bench in a way that exercises their block properly at the unit level. Verification engineers, on the other hand, take a more software-centric approach. By using an interactive methodology designers can easily see what is needed to verify their block and the verification engineers can visualize the techniques and capabilities needed to verify the block, re-use the designer's unit test and incorporate new advanced techniques. This new visibility allows them to work in a common framework.

The improved accessibility this new interactive methodology offers also drives up productivity by encouraging reusability of verification components across an organization. When verification engineers operate in an environment that provides basic templates and models, they save time by using those examples as a basis for their own components. And when engineers working on other projects in an organization can simply click through the same examples or easily access and understand the verification components developed for a previous project, they can easily leverage that work to accelerate the development of verification components for their own design. This practice places everyone in the organization on a consistent methodology and dramatically simplifies the development of every verification strategy from planning to closure. Moreover, as design and verification teams become increasingly global, the use of a consistent and highly interactive methodology allows all engineers participating in a project to operate in the same environment, enhancing communication across the team and reducing time to first test from months to days.

Conclusion
Rising design complexity coupled with increasingly intricate hardware/software interactions and customers' rising demand for lower power operation are placing new demands on SoC functional verification strategies. Together these trends are threatening SoC predictability and product development schedules.

An innovative new interactive methodology offers design teams an answer to these escalating challenges. By combining expert knowledge, coverage-driven verification techniques and best practices, demonstrating them on a representative design, and giving the user easy access to those strategies across all levels of the design, this new approach promises to simplify the adoption and proliferation of new verification technologies and improve communication and reuse across functional groups.

About the Authors:
John Brennan is Marketing Director in the Cadence Kits organization. He can be reached at brennanj@cadence.com.
David Tokic is Director of VIP and Strategic Marketing, Cadence Verification Division. He can be reached at davet@cadence.com.