While base classes accelerate SystemVerilog deployment, the verification challenge continues to grow. There is a need to further advance verification productivity. Synopsys has been addressing this need by creating VMM Applications on top of the base classes. These applications allow engineers to focus on finding bugs in their designs, instead of spending time on repetitive tasks for every project. Among other tasks, the these applications address verification of registers, memory elements; data stream scoreboarding for self-checking testbenches; creation of reusable testbenches from block to chip to system-level verification; and deploying coverage-based verification planning and tracking. Recently ARM, Renesas and Synopsys announced VMM LP which expands VMM to address the emerging challenge of low power verification. VMM base classes, VMM Applications, VMM Planner specification and other VMM utilities are available for download and use at vmmcentral.org under Apache 2.0 open-source license.

Having solved the initial need for base classes, industry innovation needs to focus on building applications and automation tools to address the ever-growing verification productivity problem. This article describes the details of VMM Applications, which are built on top of the VMM base classes as shown in Figure 1.

1. Details of VMM Applications, built on top of the VMM base classes.

Register Abstraction Layer (RAL) - VMM Application
The VMM Register Abstraction Layer (RAL) is a VMM application package used to automate the creation of a high-level, object-oriented abstraction layer for memory-mapped registers and memories in a design under verification. The abstraction mechanism allows verification environments and tests to be migrated from block to system levels without any modifications. It also allows fields to be moved between physical registers without requiring modifications in the verification environment or tests.

2. VMM RAL automates high-level register and memory testing.

The RAL includes predefined test cases that can be used to verify the correct operation of registers and memories in a design under verification. Several functional coverage models are included to accurately measure how thoroughly the registers and memories have been exercised.

The RAL supports front door and back door accesses to provide redundant paths to the register and memory implementation and verify the correctness of the decoding and access paths, as well as accelerating access once the backdoor paths are set. The RAL also supports designs with multiple physical interfaces, as well as registers and memories shared across multiple interfaces.

Memory Allocation Manager (MAM) - VMM Application
This application is a memory allocation manager utility class similar to OpenVera's region() system function or C's malloc() and free(). A single instance of this class is used to manage a single, contiguous address space. This memory allocation manager is used by any application-level process that requires reserved space in the system memory. The section of memory (called a region) will remain reserved until it is explicitly released.

3. VMM MAM allows multiple, concurrent, and random masters to intelligently access a shared memory.

Hardware Abstraction Layer (HAL) - VMM Application
The VMM Hardware Abstraction Layer is a VMM application package used to abstract the communication between a testbench running on VCS and a design under verification (DUT) running on an emulator, accelerator or FPGA board.

4. VMM HAL provides power of VMM at the speed of hardware.

The hardware abstraction layer removes the testbench from the different communication mechanisms provided by various available hardware assistance platforms. The same testbench, testcases and DUT can thus be targeted to different assistance platforms without any modifications. The application package also contains a purely simulated implementation of the hardware abstraction layer that allows the testbench and testcases to be developed and the DUT to be debugged entirely within the same simulation without requiring any modifications.

DataStream Scoreboarding - VMM Application
In many verification environments, the self-checking mechanism involves the use of a transaction-descriptor storage, retrieval and comparison infrastructure called a scoreboard. The functionality of scoreboards can be generalized for different application domains. However, different scoreboards may be required for different application domains. It will be necessary to use the set of foundation classes the best correspond to the application to be verified.

5. VMM Scoreboarding automates the self-checking component of a testbench.

Data stream applications involve the transmission, multiplexing, prioritization or transformation of data items. Data stream applications include - but are not limited to - busses, bridges, codecs, switches, routers and network processors.

Performance Analyzer - VMM Application
In many designs, it is important to analyze and report on the performance of a shared resource utilization or the processing throughput of a functional unit. The shared resource may be a bus, a memory, a DMA channel or any other design element that is used by more than one initiator over a period of time. As a generic VMM package, the Performance Analyzer (PAN) is not based on, nor requires, specific shared resources, transactions or hardware structures. It can be used to collect statistical coverage metrics relating to the utilization of a specific shared resource, functional units, transactions or hardware structures. It can be used to collect statistical coverage metrics relating to the utilization of a specific shared resource.

6. VMM Performance Analyzer verifies difficult to measure performance characteristics of a design, such as QoS.

Performance is analyzed based on user-defined atomic resource utilization called tenures. A tenure refers to any activity on a shared resource or functional units with a well-defined starting and ending point. In addition to starting and ending times, additional user-edfined performance related data may be stored in the database with each tenure to facilitate the subsequence performance analysis.

VMM Planner
VMM Planner provides a plan-to-coverage-closure solution with several technologies, including plan capture and viewing, plan annotation to back annotate the coverage plan with coverage data collected from regression, and spreadsheet interface to back annotate regression data back to a spreadsheet. The coverage goals and targets are specified in a machine executable format, which is tracked in an actual simulation to determine the numeric value of the coverage delivered by a regression suite.

7. VMM Planner simplifies plan-to-coverage closure with an easy to read report.
(Click this image to view a larger, more detailed version)

VMM for Low Power Design (VMM-LP)
Based on decades of collective verification and IP experience from ARM, Renesas and Synopsys, the Verification Methodology Manual for Low Power Design (VMM-LP) documents a robust and scalable verification architecture that can be easily leveraged to quickly set up and complete verification of low power designs. The methodology addresses all functional verification aspects of power-management functions, including suggestions for static versus dynamic verification, design-for-verification techniques, and the use of assertions and coverage metrics to achieve rapid verification closure. The VMM-LP base class library source code will be made available as a free download under the popular Apache 2.0 open source license.

Open Source, Standardization, Multi-vendor Support
VMM is available via the popular Apache 2.0 license at this site. Anyone can download VMM code, learn about VMM, and participate in VMM discussion forums and blogs at this web site.

8. vmmcentral.org offers download, an active discussion forum, and a blog from Janick Bergeron.

Conclusion
Functional verification is an ever growing challenge. Verification methodology must expand beyond the base classes to help engineers address this challenge. The VMM base classes have allowed hundreds of design teams globally to focus on creating highly complex, scalable, reusable verification environments. Now, VMM Applications, VMM Planner and VMM LP allow engineers to build on this strength and further cut down verification time and find more design bugs.

About the Author:
Janick Bergeron is a Scientist at Synopsys, and the author of the Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models.
He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. His email is: janick@synopsys.com.