Design Article
Visualizing, analyzing and debugging SystemVerilog testbench environments
Bindesh Patel and Rex Chen
5/1/2009 1:25 PM EDT
SystemVerilog, and the verification methodologies that have sprung up around it, have enabled a significant leap forward in testbench automation and allow for generation of sophisticated stimulus scenarios.
This level of sophistication and automation requires a corresponding leap in debug capabilities within such environments. Advanced logging and interactive inspection provide an ideal means of recording transactions from the testbench and subsequently, allowing visualization and analysis of these transactions.
Authors from SpringSoft and Verilab look at these emerging verification techniques.
|
|
|
|
|
Navigate to related information
