Survey has designers assign ROI to verification chores

Jasper Design Automation surveyed over 50 engineers and engineering managers at DAC 2009 as part of a market research and analysis program examining how designers use formal verification across the design cycle.

Jasper reached the following conclusions:

The top four important applications that motivates designers to use formal verification for targeted ROI across the design cycle are: RTL block verification; design and IP leverage; RTL development; and silicon debug.

These are followed by architectural analysis early in the design cycle, chip integration, and low-power design verification.

Read the full Jasper survey here.