Prevailing physical verification flows are predominantly post-processing oriented, relying on post-GDSII modifications of the design. Not only do these flows lead to suboptimal results, but they can also induce expensive implement-then-verify iterations between the place-and-route and physical verification tools. Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue.

A case in point is Aquantia, a leading supplier of 10G Ethernet solutions, which developed its latest IC in the advanced 40nm node. Currently, physical designers at companies like Aquantia stream out the timing-closed, post-fill design for signoff validation and may stream it back to fix any signoff errors flagged during physical verification. This time-intensive implement-then-verify loop is repeated until the post-fill design is both signoff accurate and timing clean.

To bridge this gap between the place-and-route and physical verification tools, the current methodology needs to evolve to deliver signoff-quality checking from within physical design. As an example, the current iterative implement-then-verify flow can be replaced with an integrated flow in which the physical verification tool can guide the implementation fill. Such an integration enables verify-as-you implement methodology that can significantly accelerate fill closure by delivering signoff-quality, higher-density and timing-aware fill.

This article discusses the traditional flows and their inherent challenges, establishing the need for an in-design flow that would mitigate those challenges. Lastly, the article describes the benefits of such an in-design flow using the Synopsys IC Compiler physical design solution and IC Validator physical verification solution, which enabled Aquantia to achieve significantly faster physical verification turnaround time and accelerated their time to tapeout.

Metal Fill Overview
Whether performed by the designer or by the foundry, metal fill is a mandatory step at advanced nodes to ensure manufacturability and high yield. It involves filling the empty or white spaces near the design with metal polygons to ensure regular planarization of the wafer. Foundry-mandated fill requirements stipulate that the fill density be within specified maximum and minimum parameters.

While regular planarization is crucial to prevent over or under polishing of signal routes and active circuitry, metal fill can also negatively affect timing due to increased capacitive coupling to the nearby nets. Thus, the designer must ensure that the metal fill is done without impacting timing-critical nets. In other words, the fill needs to be timing-aware. Timing-awareness is also needed when the engineering change order (ECO) arrives late in the design cycle. The ECOs require the designer to change the layout and fill around the affected area. Thus, the fill methodology should allow easy removal and re-insertion of fill without violating timing of the nearby nets.

To optimally fill the design while minimizing the capacitive coupling, foundries have responded with increasingly sophisticated requirements to achieve the requisite fill density. As an example, while the place-and-route guided track-based fill on the left of Figure 1 can potentially cause higher capacitive coupling with the adjacent signal nets, the physical verification guided staggered and signoff fill pattern on the right delivers better white space coverage while reducing capacitive coupling. Since the staggered fill is coded as signoff requirements in a physical verification runset, the resulting fill from such runsets can be called signoff metal fill.

For advanced nodes, it is also necessary for metal-fill methodology to support large hierarchical designs to enable higher productivity. Such designs can be efficiently verified with an easy way to skip re-filling a pre-filled block since, in a typical design flow, the designer utilizes pre-filled blocks supplied by IP and core providers. These providers have already carefully closed timing after metal fill insertion, and it is crucial that the timing of such blocks be preserved by excluding them from any additional fill. Figure 2 illustrates this issue. In addition, for advanced node designs, the fill sizes can easily result in multiple gigabytes of data. Since higher storage translates to higher costs, it is imperative that the fill disk footprint be as small as possible.

In summary, an ideal metal-fill flow must have the following attributes:

1. Fast and timing aware " Fast runtimes and critical net timing should be preserved while meeting the density requirements.

2. Signoff quality " Inserted metal fill must be signoff accurate.

3. Support a hierarchical methodology for large designs" Pre-filled IP and cores should be excluded from being re-filled during full chip assembly.

4. Smallest data size footprint " Crucial to reduce disk-space requirements.

Having established the requirements for an ideal fill flow, we can now evaluate existing fill approaches and identify their strengths and weaknesses. While these approaches can vary greatly across design groups, designers commonly have two point tool-driven options.

Option 1 - Metal Fill Using a Physical Verification Tool
Since metal fill is typically done after detailed routing and timing closure, designers create the GDSII of the design and then stream it out to a physical verification tool to insert metal fill to meet sign-off requirements. Fill is done during various stages of design:

First, as depicted in Figure 3a, every design block is closed for timing and then streamed out for fill to be done by a physical verification tool.

During final chip assembly (Figure 3b), all the pre-filled blocks are incorporated in the final design. Post stream out, the physical verification tool is used again to fill the remaining white spaces at the top-level.

If an ECO were to come in (Figure 3c), the designer would rip out the existing fill, stream out the design and refill using a physical verification tool.

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The pros and cons of such a flow are summarized in Table 1:

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While this flow may enable early detection of timing issues by inserting fill during design, this fill flow is still non-optimal and may result in iterations between place-and-route and physical verification. The pros and cons of this option are summarized in Table 2.

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Since both the above options suffer from expensive iterations induced by the design-signoff gap, designers need a fill flow that integrates signoff-quality verification within physical design. Such an in-design flow is described in the next section.

In-Design Metal Fill Flow for Advanced Nodes
As shown in Figure 5, by integrating a signoff tool within the timing-aware physical design environment, the in-design flow allows the designer not only to implement signoff-quality fill during design but also to assess the timing impact of such fill and make any necessary corrections from within the physical design environment.

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1. Signoff-quality metal fill during place-and-route " The integrated physical verification tool can insert fill as specified by the foundry-provided signoff runset.

2. Timing-aware fill " The inserted fill can be intelligently placed based on the timing information provided by the place-and-route tool to avoid expensive iterations involving multiple stream-in and stream-out penalties since both the place-and-route and physical verification tools are working off the same database.

3. Ease of inserting pre-filled blocks within a design for large hierarchical designs " Bounding boxes can be specified from within the place-and-route tool.

4. Smallest data size footprint " The physical verification tool can store the data hierarchically as array references.

5. Zero physical verification learning curve " The controls for fill setup, execution and debugging are available through the place-and-route tool.


Case Study: IC Compiler-IC Validator In-Design Flow at Aquantia
Synopsys' IC Compiler and IC Validator have been tightly integrated to offer an in-design metal fill flow. This integration enables an IC Compiler user to insert signoff-quality and timing-aware fill during design. The ease of setting up and executing the in-design metal fill flow along with its sign-off accuracy and timing awareness led to accelerating the time to tapeout at Aquantia. Figure 6 illustrates an example of the ease with which the Aquantia designers were able to setup and execute the metal fill flow using simple IC Compiler forms.

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As Table 3 below indicates, by using in-design metal fill with IC Compiler and IC Validator for one of the design blocks, Aquantia was able to achieve timing-aware metal fill; the timing impact of such a fill was minimal.

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Additionally, the Aquantia case illustrates that IC Validator-guided in-design fill is not only sign-off quality fill (on the right) with higher density, but unlike a place-and-route guided fill, it also provides less capacitive coupling to the nets by avoiding long running tracks (Figure 7).

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IC Validator inserts foundry-mandated multi-width fill in a single pass while the place-and-route tool requires several passes to achieve a similar fill.

IC Validator offers linear scalability over several cores to further accelerate the runtime.

Figure 8 illustrates the runtime acceleration and scalability offered by the in-design flow. As a comparison, the single core runtime reported in figure 8 is around 10x faster than the third party place-and-route tool runtime.

The in-design flow enabled further acceleration for the ECOs. Instead of streaming out and re-filling the entire design, the designers could incrementally fill just the changed area. As an example, one of the Aquantia blocks took less than 5 minutes for the incremental fill compared to more than 2 hours for complete re-fill.

Given the hierarchical nature of their designs, the in-design metal fill flow with IC Compiler and IC Validator offered Aquantia substantial benefits for inserting fill, by making it easy for the Aquantia designer to exclude metal fill from the pre-filled blocks. This maintained the timing integrity of the pre-filled IP that Aquantia integrated in their design. Figure 9 describes how the specification of the bounding boxes was easily accomplished by using the "exclude_bounding_box option in the signoff_metal_fill command to specify the excluded blocks.

By representing the fill as array references, IC Validator offered significantly reduced fill data size for Aquantia's design. Instead of replicating the fill data for multiple instantiations of a specific block, only one fill instance was stored in memory. Other instantiations were referred to the stored fill data. Figure 10 depicts sample fill data size reduction results (~2x) for one of the blocks in their design.

As the Aquantia case study demonstrates, the in-design flow with IC Compiler and IC Validator delivers faster physical verification turnaround time (TAT) by:

Eliminating expensive iterations between design and signoff by delivering signoff-quality, timing-aware fill within IC Compiler.

Boosting designer productivity with fast fill runtimes and ease of both the flow setup and execution.

Enabling efficient fill methodology for large hierarchical designs.

Requiring smaller disk space for storing the fill data.


Conclusions
Stringent fill requirements for advanced device nodes no longer make it practical to use methodologies that confine place-and-route and physical verification tools to separate silos. An in-design flow that integrates the two tools delivers faster turnaround time by eliminating expensive and time-consuming iterations. While this flow offers several features " signoff-quality timing-aware fill, fast runtime, ease of setup and execution, efficient methodology for hierarchical designs and small disk-footprint " the overriding benefit of in-design flows for physical designers is significantly faster physical verification turnaround time and faster time to tapeout.

About the authors
Steven Yang is director of physical design at Aquantia. He has led and managed many high-end and high-performance designs. Before joining Aquantia, Yang was design services director at Cadence. He also held various technical positions at Simplex Solutions and Altius, and has extensive experience in design methodology and timing closure.

Rahul Kapoor is group product manager at Synopsys, where he is focused on growing the physical design and verification business. He has successfully led numerous go-to-market product campaigns at Synopsys, Cypress and Intel. His prior experience include microprocessor R&D team leadership at Intel and semiconductor-focused Investment Banking at CSFB. Kapoor has a bachelor's degree in electrical engineering from IIT, Delhi, and an MBA from the Kellogg Graduate School of Management.