In-design metal fill key to physical verification turnaround time for advanced IC designs

Prevailing physical verification flows are predominantly post-processing oriented, relying on post-GDSII modifications of the design. Not only do these flows lead to suboptimal results, but they can also induce expensive implement-then-verify iterations between the place-and-route and physical verification tools. Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue.

A case in point is Aquantia, a leading supplier of 10G Ethernet solutions, which developed its latest IC in the advanced 40nm node. Currently, physical designers at companies like Aquantia stream out the timing-closed, post-fill design for signoff validation and may stream it back to fix any signoff errors flagged during physical verification. This time-intensive implement-then-verify loop is repeated until the post-fill design is both signoff accurate and timing clean.

To bridge this gap between the place-and-route and physical verification tools, the current methodology needs to evolve to deliver signoff-quality checking from within physical design. As an example, the current iterative implement-then-verify flow can be replaced with an integrated flow in which the physical verification tool can guide the implementation fill. Such an integration enables verify-as-you implement methodology that can significantly accelerate fill closure by delivering signoff-quality, higher-density and timing-aware fill.

This article discusses the traditional flows and their inherent challenges, establishing the need for an in-design flow that would mitigate those challenges. Lastly, the article describes the benefits of such an in-design flow using the Synopsys IC Compiler physical design solution and IC Validator physical verification solution, which enabled Aquantia to achieve significantly faster physical verification turnaround time and accelerated their time to tapeout.

Metal Fill Overview
Whether performed by the designer or by the foundry, metal fill is a mandatory step at advanced nodes to ensure manufacturability and high yield. It involves filling the empty or white spaces near the design with metal polygons to ensure regular planarization of the wafer. Foundry-mandated fill requirements stipulate that the fill density be within specified maximum and minimum parameters.

While regular planarization is crucial to prevent over or under polishing of signal routes and active circuitry, metal fill can also negatively affect timing due to increased capacitive coupling to the nearby nets. Thus, the designer must ensure that the metal fill is done without impacting timing-critical nets. In other words, the fill needs to be timing-aware. Timing-awareness is also needed when the engineering change order (ECO) arrives late in the design cycle. The ECOs require the designer to change the layout and fill around the affected area. Thus, the fill methodology should allow easy removal and re-insertion of fill without violating timing of the nearby nets.

To optimally fill the design while minimizing the capacitive coupling, foundries have responded with increasingly sophisticated requirements to achieve the requisite fill density. As an example, while the place-and-route guided track-based fill on the left of Figure 1 can potentially cause higher capacitive coupling with the adjacent signal nets, the physical verification guided staggered and signoff fill pattern on the right delivers better white space coverage while reducing capacitive coupling. Since the staggered fill is coded as signoff requirements in a physical verification runset, the resulting fill from such runsets can be called signoff metal fill.

For advanced nodes, it is also necessary for metal-fill methodology to support large hierarchical designs to enable higher productivity. Such designs can be efficiently verified with an easy way to skip re-filling a pre-filled block since, in a typical design flow, the designer utilizes pre-filled blocks supplied by IP and core providers. These providers have already carefully closed timing after metal fill insertion, and it is crucial that the timing of such blocks be preserved by excluding them from any additional fill. Figure 2 illustrates this issue.