How do you qualify netlist reduction and circuit extraction?

The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next generation designs. A real gap appears between layout extraction and circuit simulation when adding layout parasitics into the flow. A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this paper.

Moving forward to advanced technology nodes severely endangers circuit design. The International Technology Roadmap for Semiconductors (ITRS) process technology roadmap together with Moore's Law states that the number of transistors over process nodes raises exponentially, doubling approximately every second year. The number of interconnections between all these transistors and the length and complexity of the supply lines is growing at the same pace. Today, when working on design kits in 40nm and below, more parasitics need to be taken into account in order to model effects. Their impact on circuit function and performance is getting predominant: delay of a signal on a line is mainly determined by the interconnection and its physical parameters and not by the active devices any more.

In order to model interconnections, EDA tools use so-called parasitic elements (resistors, capacitors, coupling capacitors, inductors, mutual inductors and others). We call them parasitic, because they have not been designed, but their behaviour needs to be taken into account. They substantially alter the intended circuit behaviour. Moving from one technology node to the next the number of parasitics increases at least at the same pace as the number of devices: A rule of thumb is about 4 parasitics per transistor. A full-chip extraction of an advanced circuit design will therefore contain several hundreds of millions of those parasitic network components.

CAD engineers and EDA vendors seek to improve current methodologies and flows in order to get a hand on the complexity issue in post-layout simulation. They can take advantage of different techniques, which can all be combined: hierarchical accurate spice simulators, multithreaded and multicore simulation tools, selective extraction approaches, and selective back-annotating of parasitics to pre-layout simulation, improved netlist reduction.

There is not one best netlist reduction technique
Among the techniques available to improve the speed and capacity of post-layout simulation taken parasitic components into account, netlist reduction is among the most promising techniques.

Netlist reduction is the keyword applied to describe the process of transforming a netlist that contains parasitic elements into a second netlist of smaller size and less parasitic elements. In principle, we can claim that the smaller the netlist, the faster the simulation tool. Ideally, the reduced netlist should have exactly the same electrical behaviour as the original netlist. However, nothing is for free: there is a trade-off to be made between the accuracy of the applied algorithms and the degree of reduction.

On top of the complexity challenges, the most important challenges of state-of-the-art netlist reduction tools are loopholes in the definition of exchange file formats and the lack of necessary mathematical conditions in the extraction tools. A typical example for a quasi-standard exchange file format is the DSPF (Detailed standard parasitic file) format: At the time of definition, capacitive coupling, inductance and magnetic coupling was not anticipated, and we find ourselves today with at least four different ways of defining coupling capacitors in DSPF files. These loopholes could easily be closed by using the SPEF (Standard Parasitic Exchange File) format, however main industry applications run on DSPF. While these issues are only related to the format and can be solved by developing several distinct interfaces, mathematical conditions must be respected. To name one: passivity is a necessary condition. Inductors, capacitors, resistors, even combined cannot generate energy; this is a basic physical law. Most of mathematical Model Order Reduction (MOR) algorithms start off with this condition, which might not be respected by extraction tools due to numerical inaccuracies. The direct application of the many proposed MOR algorithms are therefore generally inapplicable for industrial applications.

Before reviewing today's available techniques, we can already state that there is no universal technique usable for netlist reduction. The good news is though that EDA tools can successfully apply a combination of different techniques.

We can distinguish four categories of approaches used in industrial tools: filtering, recursive star-triangle transformations, delay-oriented local operations and mathematical solutions called Model Order Reduction.

Filter
The usual industrial approach to netlist reduction is the determination of threshold values. If a component has a value below or above one of the thresholds, it will be eliminated from the netlist. An example of this approach is the postulation of a g_min value, which determines a minimum admittance. Admittance values below this threshold are dropped. This simple, but effective, technique can be applied to any of the linear parasitic components. For obvious reasons, those techniques are called "filtering techniques". They are very efficient when the values of the parasitics vary a lot. However, when all values are in the same range, it is hard to determine where to set the threshold and important errors might be introduced in the circuit. They also need to be implemented with care in order to ensure the completeness of the electrical circuit: a filtered element must not leave a hole in the netlist. With respect to accuracy it can be stated that filtering methods without any error control are relatively dangerous in the sense that filtered parasitics might have been important in their context and thus the simulation result will alter. Filtering without error control might also introduce instabilities into the circuit.