Design Challenges Drive Need for New Routing Architecture

While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below, where making a trade-off between traditional design goals and yield is becoming tougher. At the latest technology nodes, there is limited room to optimize post routing. This leads to a ping-pong effect, where one design goal is optimized while another is not, necessitating much back and forth performing multiple iterations. Simultaneous optimization of yield is becoming increasingly important in order to achieve high Quality of Results (QoR).

To illustrate this with an example, let us consider the redundant via insertion that protects nanometer designs from via failures. Classic routers insert redundant vias post timing optimization. Doing so during place and route is certainly better than inserting redundant vias during physical verification, where the timing impact cannot be estimated. However, since redundant via insertion is done after the design is already routed and optimized, there is limited flexibility for trading off timing and yield. While it is possible to preserve timing, it is often done at the expense of the redundant via rate. To achieve an efficient trade-off between yield and timing, vias and other yield optimizations such as antenna checking and fixing should be performed throughout the routing and optimization flow. In doing so, their impact can be estimated together with other design goals such as timing, area, power, and signal integrity.

To compensate for manufacturability issues related to lithography, the number and complexity of routing design rules are constantly increasing. At older technology nodes, the routing rules were primarily spacing rules between two nets. This is no longer the case. For instance, line-end and via proximity design rules describe complex routing patterns with constraints between multiple rectangles. Other new routing design rules, such as min edge rules, are polygon-based in nature. Implementation of such litho-related design rules can in some cases over-constrain classic routers, causing difficulty with convergence and design rule checking (DRC) closure. Polygon-based techniques can better handle such design rules, while a new routing architecture that supports the use of multiple weightings and soft rules can better address litho-related challenges without over-constraining the router.

While it is possible to bolt yield optimizations onto classic routers post processing, doing it simultaneously is exceedingly difficult. Centerline connectivity models of classic routers impose numerous limitations to shape manipulation, limiting the ability to carry out geometry optimization for addressing modern design rules. To free the router from such artificial constraints, a realistic intersecting connectivity model is needed. Classic gridded routers represent the routing search space by a maze grid. With the latest technology libraries, performing operations such as off-grid pin allocation has become challenging for gridded routers. Gridless routers came to the rescue, but their flexibility comes at the expense of speed and the ability to handle large designs. The solution lies with a routing technology that marries the speed of the gridded routers with the flexibility of the gridless ones by allowing the generation of additional routing grids dynamically and on the fly for off-grid operations.

When evaluating new routing technology needs, and how they can be applied to reach maximum potential, the available computing resources should be taken into account, as runtime is constantly challenged due to ever-increasing design size and design rule complexity. As multi-core systems are becoming mainstream, there is an opportunity to leverage these resources by deploying advanced multi-core software and optimized information technology (IT) solutions that can deliver breakthrough productivity increases.

State-of-the-art routing technology is now required to handle complex design rules and to trade-off yield and other design goals efficiently at advanced process nodes. Moreover, with the increase in process variation, routing optimization should be variation-aware for robust, multi-corner clock tree design and route topology creation. Last but not least, routing technology must be fully integrated with placement, clock tree, and multi-corner multi-mode optimization in order to achieve higher QoR.

Steve Meier is currently vice president of Engineering for the IC Compiler R&D Group at Synopsys.