Viewpoint: IC technology choice moves in multiple directions

While this is (and had better remain to be) the main focus for the technology R&D sector and the semiconductor equipment market, it is much less the focus of the semiconductor companies' business units and product groups. These future technology nodes are not going to do much for their business success in the short-term.

The most appealing and successful electronic products that we enjoy today, are powered by chips that are made in technologies of 180nm to 90nm with a few in 65nm. One can safely bet that the next greatest gadget will be a market success not because its chips are going to be fabricated in 45nm or 32nm, but because of better product design, software functionality and integration, and cool user interface.

In the past two decades, semiconductor products have been moving in one technology direction shrinking down feature size. When a semiconductor company's current product went to tape-out in 1.0 micron, its next product (usually 18 months or more later) would be designed for 0.8m, then to 0.6/0.5m, 0.35m, and so on.

Up, down and sideways

Process migration is not only occurring, but it is occurring in all directions: down, up and sideway.

The down path is already known for example, memory companies continue to strive to shrink memory cell size as the memory market is driven by density and cost per bit. But other IC products such as system on chips for various industries are looking at different factors to improve and differentiate.

Since the new features size doesn't necessarily equate with lower die cost, cost considerations might actually lead product teams to opt for using an older process technology that is now mature, has multiple fabrication sources and is priced more competitively. Existing products that sell in high volumes and enjoy a solid market can be ported to another foundry within the same process node, to create an alternate source driven by cost and risk management.

In many cases, new IC designs are, in fact, specialized derivatives of existing designs. Each such new derivative might address a specific market, and requires special process flavor that again requires porting within the same process node, for example low-power process, high-voltage process or a non-volatile memory process, etc.

It's the IP stupid

Silicon IP is now playing an increasingly important role, both physically — taking up significant part of the SOC, and functionally enabling connectivity, higher integration levels and total product competitiveness.

Availability of the right IP at the right time can sometimes dictate technology and foundry choice by semiconductor companies. Conversely, IP vendors need to make their choices about which process to implement their IP in. Often, the first implementation is in an advanced node, driven by market positioning and broader market strategy.

Later on, actual customers might request implementations in older technology nodes and processes or different foundries in the same technology node. Having already designed a first implementation, the IP vendor can port the design into that older process node implementation more quickly and with relatively little effort.

The need for process migration continues to evolve as semiconductor companies continue to explore different process technologies for their next products. However, the technology choice trajectories are becoming more varied and are influenced by many more different factors and are therefore not easily predictable as they used to be.

Those of us involved in EDA and semiconductor IP development should strive to develop architectures and flows that support and enable faster and easier porting between technologies in all possible directions to lower implementation barriers and enable a greater degree of design-reuse.