What if what-if analysis won't work at 28nm?

The what-if analysis has become a very popular technique for design teams because it allows the team to project the effects that the incremental modifications will have on the design. The what-if technique is based on hypothetical timing fixes (speeding up cells or paths for setup violations and inserting delay for hold violations). The what-if analysis can be performed within the static timing tool — which enables fast iterations. This allows the designer to improve the overall timing picture before implementing the more time-consuming ECO using the place-and-route tool. This approach has been critical — and feasible — at 90 and 65 nm. At 40 nm, where the number of timing scenarios (modes x PVT corners) is pushing design teams to the brink of too much analysis, managing the hold timing fixes is arduous at best and schedule-missing at the worst.

What is the cost of what-if?
Ideally what-if analysis identifies the ECO fixes that should be provided to the place-and-route tool such that all of the fixes can be implemented in one ECO turn. Sounds great! The reality is that since the what-if analysis is based on hypothetical timing it only provides a means to fewer timing ECOs. Implementation of timing ECOs — especially for hold timing — is a roll of the dice given the complexity of ICs. Between high cell placement utilizations, complicated clock architectures that magnify the effects of margins related to on-chip-variation (OCV), and the fact that many design teams sign-off with more than four PVT (process, voltage, temperature) corners, the what-if approach to fixing hold timing violations must be handled carefully. The number of hypothetical buffer fixes required to address the hold timing violations may push the congestion and/or utilization of the chip over the edge — leading to an increase in design size and/or dramatically affecting the schedule of the chip.

Cell utilization and complicated clock structures are not new to 40 nm or at 28 nm. Design teams have spent many years developing a feel for working around (or with!) these complexities. However, designers are only in the early stages of enabling multi-corner analysis and closure in their place-and-route optimization and analysis flows. By meeting hold timing at one to two PVT corners within the place-and-route flow, design teams must understand what impacts these other PVT corners will have on the chip's hold timing picture. After layout, the effects of the multi-corner analysis may lead to more hold fixes than expected. Inserting buffers to fix the hold violations may lead to degradation in performance by impacting the setup timing. In addition to the upsizing required for setup fixes and buffer insertions for hold fixes, meeting the slew requirements is also a key factor in timing closure. These steps may lead to die size increase, power increase and unanticipated schedule delays.

Despite the potential drawbacks of this process, it is well understood and has worked for years. The majority of design teams perform timing closure using perl scripts to analyze timing reports. These scripts, which are often evolutions of scripts developed many chips and/or years ago, produce what-if analysis or ECO scripts that designers can use within their timing analysis environment. By analyzing the impact of ECOs before implementing them in the place-and-route tool, designers may avoid the "timing closure ping-pong" scenario where ECOs that fixed the original timing violations created new timing violations. But will it continue to work at 28nm and beyond?