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Generating AMD microcode stimuli using VCS constraint solver
Gregory Tang and Rajat Bahl, AMD Inc., Alex Wakefield and Padmaraj Ramachandran, Synopsys Inc.
7/14/2010 4:55 AM EDT
As microprocessor designs have grown considerably in complexity,
the use of hand-written directed tests in verification has dwindled.
Automated random test generators that cover the stimulus space more
efficiently have emerged in their place. These random test generators
create microcode test sequences, emphasizing the distribution of stimuli
across all meaningful values for opcodes and other instruction
attributes. Traditional methods randomize instruction fields
sequentially, which often results in verbose, redundant code and limited
control over distributions.
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
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