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eegeezer
eewiz
I think in-design physical verification is a good approach to reduce cycle ...
Using in-design physical verification to reduce tapeout schedules
Tadahiko Yamamoto, Norikazu Ooishi, Toshiba Corp., and Kerstin McKay, Synopsys Inc.
7/30/2010 4:23 AM EDT
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.
Synopsys' IC Validator, combined with IC Compiler, provides both the functionality and performance required for an in-design physical verification solution. This paper highlights the advantages of using IC Validator at several stages of the Toshiba design flow for both DRC and metal fill. Toshiba demonstrates the runtime and flow benefits of using IC Validator to find and debug DRC issues during the implementation stage. Toshiba also shows a significant reduction in total schedule time for completing DRC and metal fill using IC Validator.
To access the full article (in PDF format), click here.
About the authors:
. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp.
. Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp.
. Kerstin McKay is Director, Corporate Applications Engineering, at Synopsys Inc.
Synopsys' IC Validator, combined with IC Compiler, provides both the functionality and performance required for an in-design physical verification solution. This paper highlights the advantages of using IC Validator at several stages of the Toshiba design flow for both DRC and metal fill. Toshiba demonstrates the runtime and flow benefits of using IC Validator to find and debug DRC issues during the implementation stage. Toshiba also shows a significant reduction in total schedule time for completing DRC and metal fill using IC Validator.
To access the full article (in PDF format), click here.
About the authors:
. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp.
. Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp.
. Kerstin McKay is Director, Corporate Applications Engineering, at Synopsys Inc.
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eewiz
7/31/2010 5:58 PM EDT
I think in-design physical verification is a good approach to reduce cycle times. All implementation tools have DRC rules given to them so these rules are followed during implementation. But if an in-design verification is required, doesnt show the inability of the implementation tools to follow the DRC?
In Short Synopsys created a partially working implementation tool, and to fix the tool flow, they made another tool. Lol. :). Anyways the final DRC/LVS signoff market is almost fully captured by Mentor Calibre. So I guess this is 1st step by synopsys towards capturing the market.
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eegeezer
8/2/2010 10:46 AM EDT
eewiz,
I disagree. Synopsys' implementation tool does exactly what it is supposed to do. What In-Design does is allows users to run "final quality" or "signoff-level" verification from inside the design flow, hence the name "In-Design". The industry is trending away from "correct by construction" towards "detection and correction" from within the design space. When designers run the implementation tool drc checker, it's checking basic routing checks. Then they give the design to the final verification group who run the full set of complex foundry rules. What In-Design does is allows the user to run these final foundry rules within the design space, called by the implementation tool to catch problems earlier and from within the design space. If the implementation tool was responsible for meeting and then checking for all these complex rules, it would take forever to finish this step. It's better to find the 25-50 complex rule errors with a fast verification tool than try to make the implementation tool avoid every scenario, then check to make sure it's done a good job.
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