Design Article
Product How-To: Interoperability comes to EDA
Paul Double, founder and CEO of EDA Solutions
10/3/2010 11:27 PM EDT
Viewing errors
To view DRC errors, the designer clicks on the error in Calibre RVE, which communicates through EVI to highlight the error in L-Edit. The errors display in sequence, and the designer resolves each one in turn in L-Edit, optionally re-running DRC.
The advantages of interoperability are even greater when cross-probing, especially during LVS. EVI supports both tools by requesting a given net in the layout or schematic and highlighting it in L-Edit and S-Edit. EVI can also query RVE for the location of particular devices in the layout or schematic by device name or from the cursor’s current position. Figure 3 shows net highlighting with different net layers in different colors.
When tracking down shorts and opens on complicated nets in layout, EVI can highlight a net by marking only specified layers or by marking each layer of the net in a different color. Calibre RVE’s advanced short isolation function can minimize the short network to make the short easier to find.
Designers can also browse extracted parasitic results in Calibre RVE and L-Edit/S-Edit, sorting parasitic results by net name or by value to find those nets of greatest interest. EVI can highlight the resistance, capacitance to substrate, and coupling capacitance in the layout or schematic. This allows designers to pinpoint the specific layout geometry causing the largest parasitics, then modify the layout to minimize any parasitic effects.
About the author:
Paul Double is the founder and CEO of EDA Solutions.
After gaining a B.Sc. Hons. in Physics and Electronics at the University of Warwick, UK, Paul started his career in IC Design with Phillips Semiconductors (now NXP), eventually moving into product management. Paul then spent eight years in Design Consultancy and EDA Software sales management, first with Rood Technology, then later with Acapella. It was at Acapella Paul first gained experience with the Tanner tools and came to fully appreciate the benefits of MOSIS MPW services.
In 2001, Paul founded EDA Solutions to further the interests of both Tanner and MOSIS throughout Europe. In this time Tanner’s sales in Europe have increased almost 400 percent, with Tanner now a serious rival to the other leading analog design tool providers.
To view DRC errors, the designer clicks on the error in Calibre RVE, which communicates through EVI to highlight the error in L-Edit. The errors display in sequence, and the designer resolves each one in turn in L-Edit, optionally re-running DRC.
The advantages of interoperability are even greater when cross-probing, especially during LVS. EVI supports both tools by requesting a given net in the layout or schematic and highlighting it in L-Edit and S-Edit. EVI can also query RVE for the location of particular devices in the layout or schematic by device name or from the cursor’s current position. Figure 3 shows net highlighting with different net layers in different colors.
Figure 3: Net highlighting with net layers in different colors
When tracking down shorts and opens on complicated nets in layout, EVI can highlight a net by marking only specified layers or by marking each layer of the net in a different color. Calibre RVE’s advanced short isolation function can minimize the short network to make the short easier to find.
Designers can also browse extracted parasitic results in Calibre RVE and L-Edit/S-Edit, sorting parasitic results by net name or by value to find those nets of greatest interest. EVI can highlight the resistance, capacitance to substrate, and coupling capacitance in the layout or schematic. This allows designers to pinpoint the specific layout geometry causing the largest parasitics, then modify the layout to minimize any parasitic effects.
About the author:
Paul Double is the founder and CEO of EDA Solutions.
After gaining a B.Sc. Hons. in Physics and Electronics at the University of Warwick, UK, Paul started his career in IC Design with Phillips Semiconductors (now NXP), eventually moving into product management. Paul then spent eight years in Design Consultancy and EDA Software sales management, first with Rood Technology, then later with Acapella. It was at Acapella Paul first gained experience with the Tanner tools and came to fully appreciate the benefits of MOSIS MPW services.
In 2001, Paul founded EDA Solutions to further the interests of both Tanner and MOSIS throughout Europe. In this time Tanner’s sales in Europe have increased almost 400 percent, with Tanner now a serious rival to the other leading analog design tool providers.
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John McGehee
10/7/2010 12:07 PM EDT
One of the most pernicious problems with tool interoperability is file skew--a prerequisite file, like a library or a verification result that is out of date. Once it gets into your data, file skew causes subtle errors that necessitate a tremendous amount of rework.
How does your Tanner-Calibre interface address file skew?
I share what I know about IC design flow control at
http://www.voom.net/controlling-your-ic-design-flow
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Joseph C Davis
10/14/2010 12:36 PM EDT
Mentor welcomes interactions between Calibre and third party tools, which is why we have the Mentor OpenDoor partner program to ensure access for other EDA vendors, and quality interfaces for our mutual customers. Quality assurance testing and certification is a big part of that program. Consequently, we feel obliged to inform readers when those expectations are not met.
Tanner EDA is currently not a participant in Mentor’s OpenDoor program, and the External Verification Interface described in this article is not validated or supported by Mentor Graphics. With the growing complexity of advanced verification flows, users should be concerned about errors in the transfer of data between tools, and they should expect that interoperability interfaces are thoroughly tested by all the vendors whose tools are party to the exchange.
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Dr DSP
12/20/2010 8:27 PM EST
Seems like the headline claim " Interoperability comes to EDA" is way too big for the article. How about "EDA Interoperabilty is 1% improved now" instead...
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