Restoring the artistry of analog design

The fact is that analog design is the most difficult and detailed kind of electronic design. The scope of variables to be managed, the extreme sensitivities to circuit constraints, and the quality of results required make analog as much of an art form as it is a science. The engineers that choose to do analog design learn their craft over time and become experts in the nuance of each analog circuit – truly artisans in every sense of the word.

So, it is little wonder that analog design flows have resisted automation. There have been attempts of course. But most were either not generically applicable or required so much work to set up that they failed to deliver any productivity gain for seasoned analog designers. As a result, the basic analog design flow has remained constant for years.

Unfortunately, the increasing complexity of silicon processes and the pervasive growth in mixed-signal designs have combined to swamp analog design teams. As more projects pile on their plates, analog designers don’t have time to practice the creativity that originally attracted them to the field. To restore the artistry to analog design, new tool automation should focus on these major areas: design optimization, design closure, and design reuse.

Design, verify, repeat
The traditional analog design flow is built around repetition of manual optimization and SPICE simulation. Figure 1 shows the basic outline of this iterative flow. From a given specification, a circuit topology is captured in a schematic and device sizes are calculated manually. The circuit performance is verified against SPICE models to predict expected performance in silicon. Specific design goals such as power, gain, or phase margin are achieved by manual calculation or by gut feel from experience and then re-verified in simulation. Once the end performance is met, the design is passed on to a physical design engineer to complete the layout, perform design rule checks and layout vs. schematic verification. The layout engineer then passes the extracted physical design information back to the circuit designer to recheck the circuit operation in SPICE. When physical effects cause the circuit to miss specifications, several more iterations of this circuit-to-layout loop may be required. This process is repeated for each analog circuit design, even to make a relatively simple specification change.