New IC verification techniques for analog content

Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these designs increases as designers integrate more functions such as WiFi, Bluetooth, 3G, GPS, and audio. The difficulty of verifying these designs is compounded by the fact that the chip designer may be including analog IP from outside sources. The chip designer might not have any analog background. This situation requires fast, robust, automatic verification of analog design rules. Traditional methods of verification are inefficient and error-prone.

Special needs for analog circuits
Analog circuits have a number of special requirements. A simple example is matched devices. Analog circuits rely on matched devices having the same electrical characteristics within a very tight tolerance. This requires a lot more than matching transistor widths and lengths. To minimize manufacturing variances, matching devices must be laid out close together. The devices must also be placed symmetrically and in a similar local environment to avoid imbalanced lithographic distortions and directional manufacturing process differences.

Proximity and symmetry can be checked with a traditional DRC tool, but how can a designer recognize which devices to apply the checks to? Designers use marker layers to identify circuitry that require special rules but marker layers have several deficiencies.

First, and most obviously, marker layers can be misapplied. An analog device without an analog marking layer will not be properly checked. Also, it is very easy to mistakenly place marker layers over circuitry that should not have them. Second, marker layers do not have enough information to allow sophisticated checks: they indicate only that a particular device must be matched to some other device, but not to which one.

Figure 1 is a schematic for a matched pair of MOS devices and a partial layout that can be used to demonstrate the rules for diffusion (blue) and poly (red) layout. Examples of traditional or generic rules might include using vertical gates only, placing two dummy poly gates with the same channel length in the same diffusion between the devices and the end of the diffusion, ensuring the width, length, and spacing of all the poly lines are the same.



A programmable electrical rule checker, such as Calibre PERC, can be used to check these rules without relying on marker layers. The circuit analysis feature automatically recognizes analog circuits, either from the schematic or from the layout (or both), and identifies specific devices. Other parts of the tool apply special measurements or customized layout (DRC) rules to enforce the analog layout rules.

Circuit analysis finds devices that are required to match by applying connectivity rules. The first simple rule is finding devices of the same type and size attached to the same supply. This simple rule will find many “extra” devices that do not need to be matched. Further circuit analysis rules are applied to weed out these “extras” until a list of matched pairs is created. These rules can be based on extensive connectivity analysis, device types, cell names, and net names.

The list of matching devices is converted to a list of matching “seed shapes”; in this example, the poly gates of m1 and m2. This list is then passed to the layout checking portion of the tool. The first layout check is to ensure that the poly gates of the matched pair are in the same well. (As drawn in the example, the gates are on the same active. Although common, this is not a hard requirement.) This check is done with simple DRC Boolean operations. Devices that should be matching but are in different wells are flagged.

Next, Calibre eqDRC operations are used to measure the counts, spacings, widths, and lengths of all the poly lines. The minimum and maximum of every measurement is stored as property on the well polygon. It is then simply a matter of checking that minimum value is equal to the maximum value for each of the measurements (space, width, and length) and that the count of poly lines per device is the same. Any differences are flagged as a violation.

To check that two dummy poly gates with the same channel length are between the devices and the end of the diffusion, designers would differentiate between the device gates (the “seeds”) and the dummy polys with simple DRC Boolean operations. Then, they use an eqDRC operation to count the dummy polys between end of the diffusion and the devices.