New IC verification techniques for analog content

Matching device routing symmetry
In analog/mixed-signal (AMS) designs, predictability of device performance is very important. A more stringent symmetry check, often required in analog circuits, verifies that the entire interconnect routing and all layout associated with matching devices is similar within some tolerance. This symmetry is critical because asymmetrical layout will lead to differences in resistance and capacitance and possibly device characteristics, causing device performance mismatch. This check is also referred to as a “butterfly” check because if the design could be folded like butterfly wings, the two sides should match.

In the previous example, all the measurements to be checked are predetermined. In the butterfly check, only the layers to be checked are predetermined. This allows us to cover the cases where we are not sure exactly which measurements are critical.

Figure 2 shows a routing asymmetry. The two routes identified by the orange circles are at different distances from the device, potentially leading to differences in the RC network affecting the performance of the design.



As in the previous example, Calibre PERC circuit analysis finds devices that are required to match. Once the layout versus schematic (LVS) and circuit extraction is complete, the tool then performs netlist topology analysis to identify the matching devices and converts them into a list of matching seed shapes.

In the previous example, the DRC and eqDRC operations that performed the layout checks were applied to all matching sets, simultaneously. In the butterfly check, the layout checks must be applied individually per device pair. This requires that designers process the device pairs with a program. Calibre PERC provides a framework for doing this with TCL as the programming language. The framework supports direct access to geometry and device data as well as the ability to execute DRC and LVS operations.

The “center of mass” of each device pair is calculated from the seed shapes coordinates. Geometry operations are then used to determine the gate direction. A “clip region” around the center of mass is then created. The clip region can extend beyond the gates by different amounts in the direction along the gate and across the gate. To produce the clip of the layout, a DRC AND operation is applied to the clip region and individually to each layer that affects behavior of the matched set. The processed layers include the devices, interconnect, wells, diffusions, implants, and contacts. This results in a layout that consists of only one matched set and nearby geometry.

Using the center of mass and the gate direction, designers determine the symmetry line. Calibre provides a DRC operation that flips layout around an axis of symmetry. A standard DRC XOR of the original clip and the flipped clip identifies any asymmetric layout.

If a tolerance in variation is allowed, a DRC UNDERSIZE and OVERSIZE operation by the amount of the tolerance will eliminate any small differences. DRC and eqDRC operations can be applied to eliminate duplicate error reporting and tag error markers tags to identify the matching device group and the layers to which the shapes belong.

The advantage of using the Calibre PERC framework is that, once the rules are coded by the programming API, these checks can be automated, replacing manual and visual debugging.