Matching device load symmetry
Consider the trivial CMOS op-amp circuit in Figure 3
. For the circuit to operate properly, the matched pair of input transistors M1 and M2 must drive the same load. For the DC operation case, the load is the total resistance to ground. For AC operation, the load is the total RCL circuit to ground. We will cover the simpler DC case; the PERC tool is capable of verifying both the DC and AC load requirements.
Figure 3: CMOS op-amp circuit.
Again the first verification step is circuit analysis. In this case, we want to identify more than the matching devices; we need to identify specific uses of matched devices. PERC allows several approaches depending on what criteria are used to identify the specific use. One example is specifically looking for op-amp circuits. Circuit analysis accepts subcircuit definitions in standard SPICE format and searches the entire design to identify instances of the subcircuit.
Once the instances are identified, the next step is to calculate the resistance from M1 to ground and M2 to ground. The resistance from M1 to ground is the sum of the interconnect resistance from M1 to M3, the resistance through M3, and the resistance from M3 to ground.
The resistance of M3 is calculated as part of device extraction. In the PERC framework, device extraction can be done for all devices as a part of circuit extraction from layout, which is the first step in the flow. Device extraction can also be done “on the fly” after the circuit analysis step.
To calculate the interconnect resistance, designers need a standard interconnect parasitic extraction tool. PERC includes a resistance only extractor. For the AC case, Calibre xRC can be executed from the PERC framework to extract R, C, and if needed L. To save time, PERC can call the extractor on select nets rather than run extraction on the entire design.
After the individual resistances are calculated, a small TCL procedure sums up the resistance from M1 to ground and M2 to ground. The totals are compared and any differences are reported.
Mentor Graphics and TSMC jointly developed more than a dozen analog-specific checks using Calibre PERC. Each of these checks is specified in TSMC’s “Layout Rules and Recommendations for Analog Circuits.” These checks are included in TSMC’s AMS Reference Flow 1.0 for the 28-nm process. These checks verify critical characteristics of the analog components of a design. Previously, there was no automated way to verify these rules.