Design Article
Intelligently integrated physical design and verification eliminate late-stage surprises and manual fixes
Davide Casalotto, STMicroelectronics NV, Stylianos Diamantidis and Paul Friedberg, Synopsys Inc.
1/5/2011 6:48 AM EST
As device geometries and feature sizes continue to shrink, designers working at advanced process nodes are concerned that rapidly increasing manufacturing requirements are causing an unmanageable number of violations late in the design cycle, when implementation tradeoffs are fixed and tapeout schedules are on the line. Traditionally, designers have relied on physical verification to deliver the critical “last step” between design and manufacturing. In today’s demanding design environment however, this implement-then-verify approach is severely running out of steam.
In this technical article, we will present an improved approach to physical verification based on intelligent point integration with physical design. This in-design physical verification alternative enables earlier detection of corner-case design rule check (DRC) violations while the design is still in flux, ensuring that manufacturing compliance is handled as a key design consideration. In addition, integration enables automation for handling low-frequency violations, eliminating late-stage manual fixes and making it easier for designers to maintain proper design convergence to signoff. The case in point is a complex 45-nm design at STMicroelectronics using Synopsys’ IC Compiler and IC Validator products for in-design physical verification.
The physical signoff bottleneck
In recent years, the number and complexity of DRCs needed to achieve manufacturing compliance have been growing at an exponential pace (see Figure 1, below). As design size continues to increase at the pace of Moore’s Law, the computational requirements placed on physical design and verification to meet manufacturing compliance are putting significant stress on existing tools and methodologies.
Traditionally, designers have relied on physical verification (PV) to deliver the critical “last step” between design and manufacturing. In this approach, designers first reach design closure for area, timing, power and signal integrity. During place and route (P&R), an extraordinary attempt to adhere to manufacturing design rules is made via a built-in technology file that serves to guide the router to avoid violating geometries. Once design closure is reached, designers then hand-off layouts to a physical signoff team who ensure that tapeout deliverables conform to detailed foundry requirements. This step involves executing full-bore, signoff-level physical verification of the design, typically using an independent, foundry-qualified tool. Any violations detected at this late stage are communicated to the design team and manually fixed through layout editing. Designs are then iteratively re-verified and edited until final convergence is achieved.
In this technical article, we will present an improved approach to physical verification based on intelligent point integration with physical design. This in-design physical verification alternative enables earlier detection of corner-case design rule check (DRC) violations while the design is still in flux, ensuring that manufacturing compliance is handled as a key design consideration. In addition, integration enables automation for handling low-frequency violations, eliminating late-stage manual fixes and making it easier for designers to maintain proper design convergence to signoff. The case in point is a complex 45-nm design at STMicroelectronics using Synopsys’ IC Compiler and IC Validator products for in-design physical verification.
The physical signoff bottleneck
In recent years, the number and complexity of DRCs needed to achieve manufacturing compliance have been growing at an exponential pace (see Figure 1, below). As design size continues to increase at the pace of Moore’s Law, the computational requirements placed on physical design and verification to meet manufacturing compliance are putting significant stress on existing tools and methodologies.
Figure 1: Increase in number and complexity of design rules at recent technology nodes
Traditionally, designers have relied on physical verification (PV) to deliver the critical “last step” between design and manufacturing. In this approach, designers first reach design closure for area, timing, power and signal integrity. During place and route (P&R), an extraordinary attempt to adhere to manufacturing design rules is made via a built-in technology file that serves to guide the router to avoid violating geometries. Once design closure is reached, designers then hand-off layouts to a physical signoff team who ensure that tapeout deliverables conform to detailed foundry requirements. This step involves executing full-bore, signoff-level physical verification of the design, typically using an independent, foundry-qualified tool. Any violations detected at this late stage are communicated to the design team and manually fixed through layout editing. Designs are then iteratively re-verified and edited until final convergence is achieved.
Figure 2: Traditional physical verification after design closure
In today’s demanding design environment, however, this traditional implement-then-verify approach is severely running out of steam.
First, it’s important to remember that implementation tools are driven by technology files while signoff tools are driven by signoff runsets. They are separately optimized infrastructures with different architectural drivers for turnaround performance, qualification and use model. Technology files may contain interactions between IP and routing constructs that are not observable within the P&R environment and are only caught at the signoff stage. As a result, more and more violations are detected late in the design cycle, forcing numerous iterations between design and physical signoff at the worst time in the design sequence — a tapeout deadline.
Second, the manual layout fixes required for manufacturing closure are becoming increasingly time consuming and can significantly impact design convergence. Designers must apply manual changes to correct the violating geometries and/or modify the technology file to achieve a cleaner route of the entire design. They may not readily possess the immediate expertise necessary to resolve the violations and may need to consult the design rule manual or turn to a PV expert who can offer recommendations for attempting repairs. In many cases, repairs may be non-trivial, such as re-routing an entire segment through a different layer. Furthermore, any manual intervention could disturb design convergence and introduce new violations, for instance by disturbing a critical timing net. Once layout editing is completed, the full cycle required to close the design and achieve expected DRC cleanliness must be repeated again, leading to potential delays and poorer final design quality.
At advanced process nodes, challenges mandate a new approach to physical verification. Ideally, this approach should enable earlier detection of corner-case DRC violations while the design is still in flux and correction can be automated. This would ensure that manufacturing compliance is handled progressively as part of the overall design convergence towards final signoff.
First, it’s important to remember that implementation tools are driven by technology files while signoff tools are driven by signoff runsets. They are separately optimized infrastructures with different architectural drivers for turnaround performance, qualification and use model. Technology files may contain interactions between IP and routing constructs that are not observable within the P&R environment and are only caught at the signoff stage. As a result, more and more violations are detected late in the design cycle, forcing numerous iterations between design and physical signoff at the worst time in the design sequence — a tapeout deadline.
Second, the manual layout fixes required for manufacturing closure are becoming increasingly time consuming and can significantly impact design convergence. Designers must apply manual changes to correct the violating geometries and/or modify the technology file to achieve a cleaner route of the entire design. They may not readily possess the immediate expertise necessary to resolve the violations and may need to consult the design rule manual or turn to a PV expert who can offer recommendations for attempting repairs. In many cases, repairs may be non-trivial, such as re-routing an entire segment through a different layer. Furthermore, any manual intervention could disturb design convergence and introduce new violations, for instance by disturbing a critical timing net. Once layout editing is completed, the full cycle required to close the design and achieve expected DRC cleanliness must be repeated again, leading to potential delays and poorer final design quality.
At advanced process nodes, challenges mandate a new approach to physical verification. Ideally, this approach should enable earlier detection of corner-case DRC violations while the design is still in flux and correction can be automated. This would ensure that manufacturing compliance is handled progressively as part of the overall design convergence towards final signoff.
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Frank Eory
1/5/2011 4:14 PM EST
Excellent article, and nice to see that Synopsys has implemented this fix-as-you-go methodology for IC Compiler.
Engineers sometimes think the P&R tool should simply not create DRC violations in the first place, but as the author pointed out, early versions of the router tech file don't always have all the rules -- so some violations are inevitable when doing a first design in a new process node. This looks like an excellent approach to solving that problem.
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