Design Article
An RTL to GDSII approach for low power design: A design for power methodology
Aveek Sarkar, Apache Design Solutions Inc.
1/12/2011 8:12 AM EST
The statistics on infrastructure and computing needs for the Internet are sobering. The volume of data that is uploaded onto YouTube every minute of the day exceeds 35 hours of video. Facebook, if it were a nation, would be the third most populous after China and India. Amazon.com withstands onslaughts from hordes of Black Friday online shoppers by having a massive compute infrastructure that sells practically everything. All these services are enabled through the creation and maintenance of large data centers that cater to the increasing amount of content and traffic on the Internet that is driven by the proliferation of broadband and mobile handset connectivity. If you consider the Power Usage Effectiveness (PUE) metric used to judge the efficiency of servers and cooling systems, the current ratio prevalent in the industry is 1.9, this means that almost half the power in a data center is used to cool servers with only the remaining half available for the computations themselves [1].
As the compute power of handheld devices approaches that of traditional computers through the use of GHz+ processor cores and increased levels of functionality, the power signature of such devices must be carefully controlled to not only make the products commercially viable, but to make them competitive in the market. As seen in figure 1, if the power density of a handheld device exceeds a narrow band, it will be too hot and must be re-designed because a human hand will not be able to hold the device for any period of time.
So, in order to be competitive, IC designs that power data centers and mobile handheld devices not only need to control and reduce their overall power consumption, but also must excel in other metrics such as performance per watt or performance per Gbps. As consumers become more aware of the power their electronic systems consume, whether based on environmental concerns, cost sensitivity or application needs, system and component designers must re-think their design goals and methodologies. Depending on the application (server, networking, 3D graphics, handheld device, etc.), the specific area of power consumption to be addressed for a particular design can be different. For example, in a processor or SoC for a handheld device, very low levels of operational and standby power targets are critical design criteria.
The need for implementing design and circuit changes in order to achieve successful low power designs is quite apparent, as shown in figure 2. The red curve illustrates the increasing levels of power that a design generates to meet advanced functionality needs (assuming no low power approaches are used), versus the yellow curve that bounds the maximum power consumption allowed in such systems. This disconnect obviously indicates that comprehensive design, circuit, and process changes must be made to bridge the gap.
Several techniques and methodologies have emerged to target low power design needs, however they do not contribute to reducing the operational or standby power numbers. They either have a marginal impact, or come too late in the design cycle. This approach towards power is usually ad hoc and is superseded by timing, area and routing considerations.
Next: -
As the compute power of handheld devices approaches that of traditional computers through the use of GHz+ processor cores and increased levels of functionality, the power signature of such devices must be carefully controlled to not only make the products commercially viable, but to make them competitive in the market. As seen in figure 1, if the power density of a handheld device exceeds a narrow band, it will be too hot and must be re-designed because a human hand will not be able to hold the device for any period of time.
So, in order to be competitive, IC designs that power data centers and mobile handheld devices not only need to control and reduce their overall power consumption, but also must excel in other metrics such as performance per watt or performance per Gbps. As consumers become more aware of the power their electronic systems consume, whether based on environmental concerns, cost sensitivity or application needs, system and component designers must re-think their design goals and methodologies. Depending on the application (server, networking, 3D graphics, handheld device, etc.), the specific area of power consumption to be addressed for a particular design can be different. For example, in a processor or SoC for a handheld device, very low levels of operational and standby power targets are critical design criteria.
The need for implementing design and circuit changes in order to achieve successful low power designs is quite apparent, as shown in figure 2. The red curve illustrates the increasing levels of power that a design generates to meet advanced functionality needs (assuming no low power approaches are used), versus the yellow curve that bounds the maximum power consumption allowed in such systems. This disconnect obviously indicates that comprehensive design, circuit, and process changes must be made to bridge the gap.
Several techniques and methodologies have emerged to target low power design needs, however they do not contribute to reducing the operational or standby power numbers. They either have a marginal impact, or come too late in the design cycle. This approach towards power is usually ad hoc and is superseded by timing, area and routing considerations.
Next: -
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