Design Article
How to instrument your design with simple SystemVerilog assertions
Ping Yeung, Ph.D., Mentor Graphics Corp.
1/26/2011 10:19 AM EST
1. Variable declarations
First, registers used to represent special information should adhere to predefined legal patterns (i.e., number of bits on/off, gray_code, odd_parity, even_parity, one-hot, one-cold). For instance, the register declarations below require that the bus_state is one_hot encoded, individual bits in int_mask are mutually exclusive and hdl_cmd will only have the legal values. In addition, there may be legal patterns that happen very rarely. Capture them to ensure they are covered by functional verification.
First, registers used to represent special information should adhere to predefined legal patterns (i.e., number of bits on/off, gray_code, odd_parity, even_parity, one-hot, one-cold). For instance, the register declarations below require that the bus_state is one_hot encoded, individual bits in int_mask are mutually exclusive and hdl_cmd will only have the legal values. In addition, there may be legal patterns that happen very rarely. Capture them to ensure they are covered by functional verification.
Next, when registers are used as counters, they should behave accordingly (i.e., consistent with all parameters for minimum, maximum, range, value, decrement, increment, delta, underflow, overflow and so on). For instance, in the register declarations below, we want to ensure hdr_adr is within the range of 1 to 26. And for the bus_cnt, it should not underflow and overflow. For counters, it may be interesting to find out whether they have hit the high-water marks. The verification team can perform more coverage analysis but will need to know the locations of these counters, pointers to which can often be found in coverage properties.
In addition, important control registers (status, address and state) should be reset correctly and should not have X or Z bits (i.e., signals should be known and driven). For instance, the hdr_status register should be known when it is valid.
In addition, important control registers (status, address and state) should be reset correctly and should not have X or Z bits (i.e., signals should be known and driven). For instance, the hdr_status register should be known when it is valid.
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jnhong
2/3/2011 10:34 AM EST
Excellent article, Dr. Yeung. The examples you show are very practical and commonly encountered (and even more commonly overlooked, but that's another story). This is a very good foundation to start with in planning verification.
In addition, I find your writing to be wonderfully clear and concise. No fluff, very precise, and no ambiguity in message and intent. Great work!
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ping_yeung
2/8/2011 12:52 AM EST
Some readers would like to learn more about Assertion Based Verification. I would recommend the free Verification Academy (verification-academy.com) organized by Harry Foster. There is a module focusing on Assertion Based Verification.
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Dr DSP
3/11/2011 9:09 PM EST
This seems like alot of work to me. Are there any rules of thumb covering what % of design time is required to implement this?
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