datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech

Design Article

Ease production at 65nm with DFM

Jean-Marie Brunet, Mentor Graphics Corp., Mark Redford, Colin Thomas and Mark Scoones, Cambridge Silicon Radio

2/15/2011 11:23 PM EST

The challenges of production at advanced process geometries are well-known. In anticipation of reaching today's leading-edge process nodes, electronic design automation (EDA) companies and chip foundries have been developing and perfecting design-for-manufacturing (DFM) technology to address users' critical needs. However, many designers viewed these DFM tools with skepticism as they continued to get products to market without them.

Two new factors now influence the use of DFM for integrated circuit (IC) development at 65nm and below. First, foundries now require or strongly recommend DFM checks, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility—customers not employing DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume manufacturing. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.

To access the full article (PDF format) click here.


Visible improvement in critical area sensitivity is demonstrated after design correction
About the authors:
. Jean-Marie Brunet, director of DFM product marketing, Mentor Graphics Corp.
. Mark Redford, general manager, North American Operations, Cambridge Silicon Radio
. Colin Thomas, DFM technologies, Cambridge Silicon Radio
. Mark Scoones, digital physical design, Cambridge Silicon Radio




Please sign in to post comment

Navigate to related information

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)