Starting at the 40/45nm design node, DRC/DFM closure emerged as a significant new challenge to IC designers. No longer could manufacturing concerns be effectively handled with the traditional design-then-verify flow. This trend is expected to continue and worsen at the 32nm and 22nm nodes, where manufacturing closure may become a serious bottleneck in design schedules. The reasons behind the growing difficulty of manufacturing closure are explored in part 1
of this series.
The traditional flow, which consists of completing the physical design before performing physical verification checks and DFM improvements, is based on a key assumption—that the place and route tool can get close enough to make physical signoff predictable. In the past, this was a reasonable assumption and the methodology worked. But at sub-40nm it begins to break down as the previous generation routers are not designed to handle the many new and complex DRC/DFM rules.
To access the full Design Article by Mentor Graphics Corp.
(in PDF format), click here
Read also: Evolution of manufacturing closure for advanced nodes (Part 1)
About the authors:
. Ivailo Nedelchev, principal technologist, Place and Route Division, Mentor Graphics Corp.
. Sudhakar Jilla, marketing director, Mentor Graphics Corp.
Courtesy of EE Times India