In parts 1
of this series, we discuss the challenges of manufacturing closure in IC design and the new design software technologies that are needed to address the issues. This article presents several examples of how performing signoff DRC/DFM verification within the place and route environment impacts the design flow and improves time to closure.
Let's first compare the traditional design flow with one that incorporates physical verification signoff as part of design implementation. Using the conventional approach, the design is placed and routed and deemed DRC/DFM clean by the physical design team. The GDSII is streamed out and transferred to the signoff team for verification signoff while the design team continues with their timing ECOs. The signoff team will run the physical verification checks and provide feedback to the implementation team on the violations that needed to be fixed.
To access the full Design Article by Mentor Graphics Corp. (in PDF format), click here.
About the authors:
. Ivailo Nedelchev, principal technologist, Place and Route Division, Mentor Graphics Corp.
. Sudhakar Jilla, marketing director, Mentor Graphics Corp.
Courtesy of EE Times India
. Evolution of manufacturing closure for advanced nodes (Part 1)
. Evolution of manufacturing closure for advanced nodes (Part 2)