Design Article
Attofarad accuracy for high-performance memory design
Claudia Relyea, Mentor Graphics Corp.
3/30/2011 9:52 AM EDT
Limitations of current parasitic extraction technologies for memory
Traditional parasitic extraction solutions reliably model interconnect parasitics, but design closure is getting more difficult at advanced nodes because of new process effects and variability that affect functionality, performance, and reliability. Some of the parasitic modeling challenges in advanced silicon processes include:
• Local interconnect
• Multi-bias vias
• Diffusion resistance
• Elevated source/drain
• SOI support
• TSV-based 3D-IC verification.
Rule-based extractors are able to extract multimillion net designs, but they rely on heuristic models and are inherently limited in accuracy—up to 10% error for total capacitance and as much as 15% or more for coupling capacitance at 45nm. These errors can account for 5–10% error in simulation results. Designers have been compensating for these limitations by using larger guard bands for timing and signal integrity, aware that such overdesign tends to negatively affect chip performance and die-size.
Until now, field solvers were restricted to cell characterization or selected net extraction. By the nature of their algorithms, they are not capable of delivering the performance or capacity needed for anything larger than a few geometries or nets. This makes them completely unsuitable for extraction of real designs.
Some field solvers employ statistical methods which increase the tools’ capacity but still are not efficient to use for large designs. They also are problematic for device-level extraction accuracy, because the user has to manually define the device regions to prevent extracting capacitive effects that are already included in the device model. This is an error-prone process.
Although statistical tools can be tuned to a tighter error tolerance, they inherently produce outliers. Specifying a tolerance of 1% means that for a design with one million nets, as many as 3,000 nets will have an error of greater than 3% (Figure 2). There is a significant chance that a critical net is misrepresented. After all, limiting extraction in scope to a few known critical nets may indeed miss important parasitic effects on other nets.
As a result of this situation, designers have been living with an extraction discontinuity and have had to employ different extraction tools and analytical methods to model the parasitic effects in their designs. The level of abstraction imposed by traditional tools forces designers to build in extra design margins, which cancels out the benefits of moving to a smaller node in the first place. IC designers are demanding extraction solutions that deliver accuracy less than 5% to evaluate the effects of parasitics on circuit timing and functionality, without compromising performance.
Traditional parasitic extraction solutions reliably model interconnect parasitics, but design closure is getting more difficult at advanced nodes because of new process effects and variability that affect functionality, performance, and reliability. Some of the parasitic modeling challenges in advanced silicon processes include:
• Local interconnect
• Multi-bias vias
• Diffusion resistance
• Elevated source/drain
• SOI support
• TSV-based 3D-IC verification.
Rule-based extractors are able to extract multimillion net designs, but they rely on heuristic models and are inherently limited in accuracy—up to 10% error for total capacitance and as much as 15% or more for coupling capacitance at 45nm. These errors can account for 5–10% error in simulation results. Designers have been compensating for these limitations by using larger guard bands for timing and signal integrity, aware that such overdesign tends to negatively affect chip performance and die-size.
Until now, field solvers were restricted to cell characterization or selected net extraction. By the nature of their algorithms, they are not capable of delivering the performance or capacity needed for anything larger than a few geometries or nets. This makes them completely unsuitable for extraction of real designs.
Some field solvers employ statistical methods which increase the tools’ capacity but still are not efficient to use for large designs. They also are problematic for device-level extraction accuracy, because the user has to manually define the device regions to prevent extracting capacitive effects that are already included in the device model. This is an error-prone process.
Although statistical tools can be tuned to a tighter error tolerance, they inherently produce outliers. Specifying a tolerance of 1% means that for a design with one million nets, as many as 3,000 nets will have an error of greater than 3% (Figure 2). There is a significant chance that a critical net is misrepresented. After all, limiting extraction in scope to a few known critical nets may indeed miss important parasitic effects on other nets.
Figure 2: Although statistical tools can be tuned to a tighter error tolerance, they inherently produce outliers.
As a result of this situation, designers have been living with an extraction discontinuity and have had to employ different extraction tools and analytical methods to model the parasitic effects in their designs. The level of abstraction imposed by traditional tools forces designers to build in extra design margins, which cancels out the benefits of moving to a smaller node in the first place. IC designers are demanding extraction solutions that deliver accuracy less than 5% to evaluate the effects of parasitics on circuit timing and functionality, without compromising performance.
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Karen Chow
3/31/2011 1:43 PM EDT
Excellent article about using a field solver to extract from bit cells all the way up to full memory chips. Also, just saw a press release about STARC using Calibre xACT 3D to extract full SRAMs:
http://www.eetimes.com/electronics-news/4214494/STARC-assesses-Mentor-s-Calibre-xACT-3D-extraction-tool-
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