Debugging for antenna issues in copper processes

The antenna effect in IC designs has long been recognized [1] [2], but an effective solution has been a little more elusive. Unlike most traditional design rule checking (DRC) errors, antennae issues are identified based on multiple layer interactions, which in turn are based upon an implied electrical connectivity at various stages in the manufacturing cycle. While the typical antenna failure is a transistor gate in danger of being shorted or burnt, the problems actually arise from metal or via interconnects that are potentially very far away from the transistor in question. As a result, debugging for antenna issues is non-trivial, and requires extensive information about the design.

Antenna effects in copper processes
Antenna problems arise from a charge that builds up on a metal wire during manufacturing. This charge is most commonly associated with the etch process. As the charge builds, it potentially creates a voltage differential that is transferred from the metal wire to its connected transistors. If the damage is large enough, the gate-oxide can break. Even if insufficient to break the gate oxide, the antenna charge on a transistor can cause permanent damage to the gate-oxide, typically in the form of interstitials.

Unlike aluminum, antenna effects in copper processes are far more dependent upon vias than on the metallization stages of processing. This dependency is a result of the common approaches in a dual damascene process. Consider the manufacturing stage of metal shown in Figure 1.



In the case of aluminum processing, the metal is deposited everywhere, and subsequently etched away to leave only the desired interconnect lines. This extensive etching produces significant charge accumulation proportional to the area (top) of the metal lines and to the perimeter (sides) of the metal lines. As seen in Figure 1, copper processing is far less susceptible, because it is the oxide that is trenched. During the trenching, there is no metal to accumulate a charge. These trenches are then filled, followed by some minor etching to remove excess metal. At this step, there is an opportunity for the copper metal regions to accumulate some charge. While the excess metal does extend beyond the trench itself, this charge can still largely be modeled as a proportion of the drawn metal layer’s surface area. Because this charge build-up is relatively small compared to the aluminum case, it is far less problematic.

After each metallization step, chemical-mechanical polishing (CMP) is applied. During the CMP process, the wafer (including all the metal applied to that point) is grounded. As a result, any remaining charge on the metal is removed. Damage to the transistor prior to the CMP stage, however, still remains. This makes the transistor more susceptible to charge build up at subsequent via or metal manufacturing stages. Because each transistor ultimately sees different metal connections across the design, each transistor has a different probability of failure. For this reason, the standard error result for nanometer process antenna rules is the individual transistors that are likely to fail.

While the metallization manufacturing stages in copper is far less susceptible to the antenna affect than the aluminum process, there is another step that also introduces antenna charges—the via processing step (Figure 2).



In this case, as the vias are trenched from the oxide, the lower-level metal is briefly exposed to the charge from the etch. This charge is proportional to the area of the vias on the metal line. Ironically, as we continue to add more vias to minimize void issues, CMP issues, or mask alignment issues, we are at the same time adding more charge, and potentially putting more transistors at risk of failure due to the antenna effects. In the case of copper, charge build-up due to vias is typically greater than the charge at the actual metal stage, and, as a result, is usually the largest contributor to antenna failures.