Design Article
Design optimization of flip-chip packages integrating USB 3.0
Rod Duzinski, Mentor Graphics Corp.; Manoj F. Nachnani, Enabling Solutions, Inc.
5/11/2011 9:45 AM EDT
IE3D model
The next step in the process is to export the trace geometries, including the package stack, up into IE3D for 3D EM modeling. The export is done using AGIF, an interface between the package design software and IE3D.
Figure 3 shows the extracted model in AGIF. AGIF is also used to set up the 3D model. The database imported does not have solder bumps or solder balls; these are defined in AGIF interface. Thickness for various conductor layers is also defined in AGIF. Ports are defined automatically in AGIF. The final 3D model that is generated in AGIF is as shown in Figure 4.
Figure 3: AGIF interface with Package Design Software design database
Figure 4: 3D view of IE3D model
Next: Simulation
The next step in the process is to export the trace geometries, including the package stack, up into IE3D for 3D EM modeling. The export is done using AGIF, an interface between the package design software and IE3D.
Figure 3 shows the extracted model in AGIF. AGIF is also used to set up the 3D model. The database imported does not have solder bumps or solder balls; these are defined in AGIF interface. Thickness for various conductor layers is also defined in AGIF. Ports are defined automatically in AGIF. The final 3D model that is generated in AGIF is as shown in Figure 4.
Figure 3: AGIF interface with Package Design Software design database
Figure 4: 3D view of IE3D model
Next: Simulation
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docdivakar
6/13/2011 7:35 PM EDT
Nice article BUT one request: if you refer to numbers in the figure, PLEASE make the figures larger so we can see what they are! The improvement in 15dB point is some what ambiguously pointed to filling the via though I agree it improves marginally. It is the additional ground vias in the return path which is well a known practice in highspeed design.
One thing your article completely ignores: USB 3.0 has higher max current draw, 900mA @5V DC. The corresponding flip chip interconnections and the package substrate designs have to take into account the current density & electromigration effects at the flip chip to substrate interface. So what is supposedly a good signal integrity-verified design does not automatically guarantee a reliable design.
Dr. MP Divakar
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