Design Article
The best of both worlds
Jafar Safdar, Synopsys, Inc.
5/31/2011 3:40 AM EDT
Physical datapath examples
. ARM cores
ARM cores are used extensively in high-performance mobile and communication products. The ARM Cortex-A8 processor’s NEON unit process multimedia applications and include blocks such as video encode/decode, 2D/3D graphics, gaming, audio processing, image processing, etc. In the NEON unit, the 19 blocks highlighted in Figure 5, used IC Compiler RP constraints for a physical datapath implementation that reduced total negative slack (TNS) by 20x.
Figure 5: Physical datapath - ARM Cortex-A8 processor’s NEON block (Source: ARM - SJ SNUG 2008)
Next: Summary
. ARM cores
ARM cores are used extensively in high-performance mobile and communication products. The ARM Cortex-A8 processor’s NEON unit process multimedia applications and include blocks such as video encode/decode, 2D/3D graphics, gaming, audio processing, image processing, etc. In the NEON unit, the 19 blocks highlighted in Figure 5, used IC Compiler RP constraints for a physical datapath implementation that reduced total negative slack (TNS) by 20x.
Figure 5: Physical datapath - ARM Cortex-A8 processor’s NEON block (Source: ARM - SJ SNUG 2008)
. Clock structure
In this example, RP constraints were used during clock tree synthesis to build clock structures with straighter routes. Figure 6 shows stacked groups of flops driven by the same leaf nets. The clock structure described using RP constraints reduced clock buffer area by 30 percent, the number of clock buffers by 10 percent and clock switching power by 8 percent.
In this example, RP constraints were used during clock tree synthesis to build clock structures with straighter routes. Figure 6 shows stacked groups of flops driven by the same leaf nets. The clock structure described using RP constraints reduced clock buffer area by 30 percent, the number of clock buffers by 10 percent and clock switching power by 8 percent.
Figure 6: Physical datapath - Clock structure (Registers, ICGs)
. Multiplexer structure
Here, RP constraints were used to create a 32-to-1 multiplexer, using 4-to-1 and 2-to-1 multiplexers. The 128-bit wide 32-to-1 multiplexer structure with structured placement and straight routes shown in Figure 7 delivered 50 percent better timing and 30 percent smaller area.
Figure 8: Physical datapath - Crossbar switch
. Multiplexer structure
Here, RP constraints were used to create a 32-to-1 multiplexer, using 4-to-1 and 2-to-1 multiplexers. The 128-bit wide 32-to-1 multiplexer structure with structured placement and straight routes shown in Figure 7 delivered 50 percent better timing and 30 percent smaller area.
Figure 8: Physical datapath - Crossbar switch
Next: Summary
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Daniel Payne
6/2/2011 10:32 AM EDT
Good article, datapath and compiled layout makes a lot of sense. In fact an entire company was formed around this very concept called Silicon Compilers in the 1980s, then acquired by Mentor in the early 1990s. There were two compiler tools: Genesil and GDT. Earlier while at Intel I wrote my own layout compilers to produce parts of a Graphics Chip automatically.
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