3-D IC design: New possibilities for the wireless market

Today’s mobile devices are about having everything in the palm of your hand, at the touch of a button—from Internet browsing and e-mail to watching high-definition TV or using a GPS. Increasing demand for multimedia features translates into complex design requirements, such as higher performance with reduced power in an ever-smaller footprint.

Design teams have two choices: either shrink the node or innovate some alternative to address the “more than Moore” trend. With development costs heading toward $100 million for the 32-nanometer process node, for example, monolithic mixed-signal SoCs are increasingly challenging and time-consuming to develop.

Design teams are looking for alternatives to speed time-to-market and reduce costs, and some are finding that using 3-D ICs with through-silicon vias (TSVs) represents the most practical way—or perhaps the only way—to handle design complexity and maximize performance and speed. 3-D ICs promise to meet market demand for miniaturization, higher speed and greater bandwidth, as well as lower latency and power consumption. That makes the move from 2-D to 3-D a natural choice.

The question today is not whether 3-D ICs will be designed and built, but whether design teams (outside of a handful of large semiconductor companies) will have the EDA tools and infrastructure support required to make 3-D-ICs cost-effective.

Not a new concept

Despite the recent buzz in the industry about 3-D technology, the concept is not new. Indeed, 3-D packaging has been around for years, in the form of stacks of dice with wirebonds, package-in-package (PiP) design and package-on-package (PoP) design, to name a few. PoP is a widespread configuration that combines a stack of memory modules atop an application processor or digital baseband. Open up your Apple iPhone 3 or your iPad, and PoP technology is already there.

Other 3-D packaging solutions—such as embedded dice in laminate, or rebuilt waferlike fanout wafer-level packaging—improve signal integrity, shorten interconnects and reduce line/space for rerouting, thus shrinking the package footprint. Though all of the above configurations are 3-D at the packaging level, none of them use TSVs.

Think of a TSV as an additional layer that helps extend the 3-D packaging to the IC level. With their short interconnects and better electrical performance, TSVs could have a huge impact on total system performance and power. TSVs can be inserted at the bond pad level (via last-in wafer-level packaging) or at the global interconnect level (either via middle back-end-of-line or via first front-end-of-line) by foundries.

For a global interconnect TSV, die stacks are connected not only at the bond pad level, but also at the IP block or memory bank level. This type of TSV enables true heterogeneous integration of die stacks using the third dimension in addition to the x-y direction, allowing optimized interconnections and better electrical performance. Dice interconnected using this type of TSV are closer to SoC/IC than system-in package (SiP) and, hence, are better referenced as 3-D ICs.

TSV technology is actually a convergence of silicon and packaging with the design, making it possible to conceive and design new architectures. To benefit fully from 3-D IC TSVs and make this technology cost-effective, a different 3-D architecture needs to be evaluated at a very early stage.

TSVs have an unclear technology road map, however, and methodology convergence is lacking because of a gap between the TSV technology process and TSV system design. Thus, 3-D IC TSVs represent a new paradigm, for which designers must modify their thinking and look beyond the 2-D constraints of classical Moore’s Law design.

There have been, and will be, multiple steps along the path to true 3-D IC packaging with stacked dice and through-silicon vias. Click on image to enlarge.

Major applications that would use 3-D ICs with TSVs are those that require speed, bandwidth and power optimization. CPUs, GPUs and routers would adopt this technology for speed and bandwidth gains. Performance gains will lead to more competitive end products for which companies can ask higher prices, and those premiums might offset the additional cost that early 3-D configurations will demand.

Graphics designs that demand very wide buses and multicore designs that require high bandwidth to the memory will also be early adopters of 3-D technology, even at the higher initial unit cost.

Set-top boxes, DVRs and HDTVs are other promising applications for 3-D IC technology. They constitute a cost-sensitive segment, but in exchange they offer high volume.

The real drive behind 3-D volume production will come from the mobile market, especially smartphones. With more than 5 billion mobile phones worldwide, this market represents attractive volumes, but cost will be the dominant criterion for TSV acceptance in the smartphone segment.

Industry requirements

With the advent of truly mobile computing, the mobile industry is searching for memory technology that can bring desktop-like computing performance to mobile devices, including support for 3-D gaming and home-theater standard 1080p, 60-frame/second video. Several estimates forecast that by 2013, SoC design starts for mobile devices will need in excess of 10 Gbytes/s of memory bandwidth—roughly what desktop machines shipping with DDR3 technology require today.

While the mobile industry requires memory technology that can support aggressive power and performance goals in the smallest possible footprint, it must also shoot for cost-effectiveness. Using 3-D ICs with TSVs is one of several possibilities. DRAM stacked with logic using TSVs—a configuration known as wide I/O—promises 2x to 4x the performance of LPDDR2 technology at half the power per bit.

Wide I/O could be the technology that meets the power and performance goals of the most advanced mobile devices, if it can be made cost-effective. The mobile industry needs to look into a number of elements to resolve the technical and business challenges that this technology brings to the table.

One of the biggest questions for any new memory technology is whether there is an industry structure to support it. Jedec efforts are under way to standardize wide-I/O DRAMs in the areas of performance, protocol, number of banks and channels, and number and arrangement of TSVs. Such standardization will create a viable market in which DRAM manufacturers can sell their standard dice to multiple customers. For their part, customers will have multiple compatible devices from which to choose.

Another concern regarding TSVs’ application with memory, in particular, is that DRAM performs poorly at junction temperatures above 85°̊ C. Keeping the memory contents refreshed at higher temperatures requires more current, which itself leads to more heating of the die. There are limits to what can be standardized, and many of the issues around assembly, test, and heat dissipation from the 3-D IC stack will need to be addressed by each customer.

One way of managing the unknowns and risks with 3-D IC technology is the use of silicon interposers. Passive silicon interposers allow semiconductor companies to gain the performance associated with 3-D IC, while mitigating risk by avoiding putting TSVs through active silicon. The silicon interposer acts as a substrate on which an active die can be connected with silicon-sized geometries that are much smaller than the interconnect on a package or pc board. TSVs are then used through the silicon interposer to connect to the package substrate below.

One of the most public announcements on the use of silicon interposers came from a large FPGA company. Rather than use one large die, the company chose to segment the technology into four separate, smaller dice to achieve greater yield. With up to 10,000 interconnect channels on each die and less than 1-ns delay, the configuration could enable performance in the silicon interposer case to be much greater than would be possible if the dice were connected side by side on a package substrate, or stacked and connected with bonding wire down to the package substrate. This silicon interposer approach promises next-generation design density using current-generation technology.

As appealing as the silicon interposer may be, it’s really just an intermediate step toward true 3-D ICs. Ultimately, miniaturization and performance goals will drive design teams to use a stacked, rather than side-by-side, approach. With TSVs, interconnect delay through the stacked active silicon should be much less than with the side-by-side interposer approach. So while the passive silicon interposer is useful for introducing the concept of TSVs to the industry, it will most likely lose ground to a stacked TSV approach as the cost and attendant risk decrease and as demand for smaller packages and higher performance increases.

Assembly continues to be a major concern in the industry. Many of the processing steps involved in the creation of TSVs can create mechanical, thermal or electrical stresses on the die being processed for TSV, and those stresses may change the properties of the device. Manufacturing test is another issue. For example, finding a method to probe TSVs with a diameter of 10 mm each and on a 50-mm grid could prove problematic. Allowing the probe head to contact more than 2,000 TSVs at a time without damage is another example. As the industry works to resolve these issues, we will surely see logic devices with TSV-connected DRAM in the next few years.

Despite the lingering challenges and unanswered questions, quite a few brave souls have embarked on this path and are working to realize the promise of 3-D-ICs for improved performance and power management in smaller footprints.

Although there’s been significant traction in this breakthrough technology over the past two years, and although there are no major showstoppers from a design or process point of view, hurdles remain to be cleared along the path to wide adoption. Those challenges include cost, the shift in the design method paradigm, system co-design, and the incorporation of new tools and new architectures. A well-defined ecosystem including foundries, IP providers, EDA vendors, and outsourced semiconductor assembly and test vendors must emerge with design kits and reference flows. Cost-effective, adoptable technological evolution and ecosystem collaboration are essential for bringing 3-D ICs with TSVs into the mainstream.

Samta Bansal is senior product manager for applied silicon realization at Cadence Design Systems Inc. She has a master’s degree in physics and a bachelor’s degree in electrical and electronics engineering from India’s Birla Institute of Technology and Science, Pilani, as well as an MBA from Santa Clara University.

Brad Griffin is director of product management for SiP, IC packaging and PCB high-speed solutions, for Cadence Design Systems’ Allegro and SiP solutions. He is a graduate of Arizona State University.

Marc Greenberg is director of product marketing for the DRAM Design IP products at Cadence. He has a master’s degree from the University of Edinburgh in Scotla