Applied tunes up transistors for DRAM makers

A series of chemistry and equipment announcements by Applied Materials today signals a step forward for DRAM manufacturers. But more broadly, the moves indicate the degree to which physics, chemistry, and the semiconductor equipment industry must cooperate to push ahead increasingly reluctant transistor performance.

The subject of all this attention is the humble silicon-gate MOSFET used in the peripheral circuitry—the address decoders, sense amps, and muxes—of advanced DRAMs. Unlike logic processes, which have converted to high-k/metal-gate MOSFETs at advanced nodes, DRAM processes have stayed with the significantly simpler silicon gate stack. The array transistors in the memory cells have undergone an intense evolution, now employing recessed channels to get adequate performance at the tiny size allowed them. But the peripheral transistors have stayed about the same through succeeding generations, until they have become the weak link in improving DRAM performance.

Applied Materials has attacked this challenge, aiming three equipment/chemistry announcements at three specific components in the peripheral transistor’s equivalent circuit. The Versa XLR (extremely low resistance) Tungsten PVD (physical vapor deposition) tool attacks gate electrode resistance and parasitic capacitance. The DPN HD (decoupled plasma nitridation, high-dose) tool increases k in the gate dielectric, allowing better switching speed and leakage control. And the HAR (high aspect ratio) Cobalt PVD tool goes to work on contact resistance.



Starting at the top, as it were, the Versa XLR is a modification of Applied’s Versa PVD tool designed specifically to produce large-grained, low-defectivity Tungsten films exhibiting low resistivity. The tool is intended for creating the Tungsten layer at the top of the gate stack, between the interconnect metal and the lower layers that end at the polysilicon gate material. Because of the lower resistivity of the low-defectivity, large-grained film, process engineers can make the film significantly thinner—350 Angstroms instead of 450, Applied claims—which in turn reduces the sidewall capacitive coupling to adjacent gate structures.

Moving straight down, the DPN HD tool is not a PVD chamber, but a plasma reactor, used to drive nitrogen into the gate oxide. Nitriding has been used since about the 130 nm logic node to improve gate capacitance. But there has been an undesirable side-effect: higher nitrogen concentrations also lead to higher threshold voltages. Applied claims to have found a way around this tradeoff, giving a combination of improved capacitance and low threshold voltage with significantly higher nitrogen concentrations—over 20 percent compared to today’s typical 10-12 percent, according to Applied global product manager David Chu. The improvement will allow continued scaling of effective oxide thickness without forcing DRAM vendors to move to a high-k gate dielectric and a metal gate electrode.

Now we move down and sideways. The third new tool, the HAR Cobalt PVD system, replaces titanium silicide with cobalt silicide at the interface layer where the tungsten contact touches the source and drain silicon.

“Titanium has been the traditional material for the silicide layer,” explained Applied metal products group director Kevin Moraes. But the nature of DRAM processes means that the contact plugs for source and drain contacts have a very high aspect ratio: instead of the typically shallower than 1:3 trenches used for logic processes, DRAM peripheral transistor contact holes are via holes with depths up to seven times their diameters. In this environment, with decreasing geometries, what was once a smooth titanium film at the bottom of the hole has become more like a little clump somewhere at the bottom of the via. The result is high, and highly variable, contact resistance. The solution, according to Moraes, is to switch from titanium to cobalt. Vapor-deposited cobalt forms a smooth, conformal film over the bottom of the contact hole, allowing creation of a uniform silicide layer and improving both contact resistance and variability. And these results provide, other parameters staying constant, higher and more predictable drive current from the transistor.

These changes in the PVD and plasma steps might appear to be tiny tweaks, of no importance to designers. But taken together, Applied says, they result in a significantly more capable peripheral transistor. DRAM makers can use this enhanced capability in a number of ways, including faster peripheral circuitry, leading to reduced DRAM latency, or smaller peripheral-circuit area at the same performance level. Given that the peripheral circuitry now occupies a large minority of the real estate on an advanced DRAM, shrinking this area could mean more room for the memory array, and hence a modest increase in density.

The story is not directly applicable to logic processes. But it is an indication of work that is going on in logic processes as well as in DRAM processes. Every parameter in the transistor model is up for examination, and even seemingly minor improvements in one number can lead to significant improvements in circuit-level performance or in cell area. These, in turn, justify a change in fab equipment, even at considerable capital expense. The low-hanging fruit is gone, and now improvements in performance and variability come dear. But at the leading edge, the industry will pay the price.