The next transistor: planar, fins, and SoI at 22nm

What’s the problem?

Planar one more time?

Not everyone agrees that the planar MOSFET is history. Principal among the dissenters is TSMC, which stated in February that it would use planar transistors in its 20 nm foundry process. There are strong arguments for this position, also held—with one major caveat—by Globalfoundries. Designers are familiar with short-channel planar MSOFETs, for all their shortcomings. This should make rescaling of cell libraries and hard IP blocks relatively straightforward. Leakage and threshold variations may be worse than at 28 nm, but the design community has tools, including aggressive power management, variation-tolerant circuits, and statistical timing analysis, to cope with these problems. And when all the issues are on the table, a foundry must do what its lead customers—FPGA vendors, networking IC giants, and to some extent ARM—ask of it.

Still, there is much skepticism. “TSMC stated that they would use a replacement-metal-gate planar process at 20 nm,” observed Novellus vice president Girish Dixit, “but that determination may have changed. HKMG can control leakage, but a planar transistor will still have inferior I-on/I-off characteristics.” If TSMC’s early adopters find themselves at a competitive disadvantage because of the planar transistor, they may force the giant into a finFET half-node. The confrontation would most likely arise in the mobile market, where ARM’s fabless silicon partners will face competition from Intel’s Atom processor, newly rejuvenated by that company’s 22 nm tri-gate process.

The rise of the fin

The next-transistor debate matriculated from a decade in the cloistered but technically accurate halls of process engineering conferences to the public forum with Intel’s May announcement of their 22 nm so-called tri-gate process. The roll-out, probably intended to counter ARM’s growing momentum in the mobile space rather than to advance the discussion in circuit design, significantly reduced the signal-to-noise level about new transistor technology.

Intel’s tri-gate device is a finFET, pure and simple. Industry experts dismiss Intel’s attempts to claim a significant difference. As such, it is one instance of a decade-old, industry-wide attack on short-channel effect—an effort that began at industry consortium IMEC at about the same time as it did at Intel. “Everyone in the industry has been developing finFET technology,” one process expert said. “The difference is in what they have chosen to announce.”

All finFET programs—indeed, all the approaches to next-transistors—rest on a single concept: the fully-depleted channel. Loosely, the concept is to give the gate so much control over the electric field in the channel that the gate can deplete the channel of carriers entirely. This of course eliminates the dominant conduction mechanism in the channel, and in effect turns the transistor off. But how to do that? In a planar device, the depth of the channel and effects from the junction formed between the drain and the silicon around it alter the electric field in the channel and interfere with depletion. Somehow you have to make the channel thin enough and far enough from the drain junction to permit the gate to fully deplete the conduction region.