3D-IC Design: The Challenges of 2.5D versus 3D

3D IC Design page 2
Since many 3D stacks combine digital and analog/RF circuitry, a strong analog/mixed-signal capability plus a robust IC/package co-design capability and PCB layout system are critical for providing a “complete” 3D-IC realization methodology. Without an integrated approach to 3D-IC design, optimizing system cost with the shortest possible turnaround time will be challenging. 3D-IC design should be a shared effort among system architects, package designers, IC designers of various dies (which probably come from different places/vendors), PCB designers, and design for test (DFT) engineers: and that calls for a system that can handle the handshake between different platforms, close collaboration between different design environments, and co-design among groups that have historically worked separately.

In addition, new capabilities such as the following will be needed to meet 3D-IC design challenges:

• System-level exploration
• 3D floorplanning
• 3D implementation (placement, optimization, routing)
• 3D extraction and analysis
• 3D design for test (DFT)

System-level exploration 3D-IC TSV technology is a convergence of silicon and packaging with the design, making it possible to conceive and design new architectures. To fully benefit from 3D-IC TSVs and make this technology cost-effective, different 3D architectures need to be considered and evaluated at a very early stage. Existing system-level exploration tools can provide early power, area, and cost estimates, and they allow what-if explorations across architectures, silicon IP choices, and foundry processes. However, these tools need to be extended to serve stacked die implementations, package, and manufacturing considerations, as well as to provide some guidance on tradeoffs that system houses would have to make among cost, power, and performance.

3D floorplanning

2D floorplanning is complex enough in today’s giga-scale designs. Adding a third dimension makes floorplanning even more challenging. Since TSVs can be very large compared to logic gates (they add more wire length and extra coupling, which is mitigated by keep-out zones that add area) a TSV-aware 3D floorplanner must allocate optimized TSV resources with respect to logic gates.

Figure 5: Planning, implementing, and verifying 3D-ICs in a Cadence environment

Additionally, TSV-aware 3D floorplanning must provide an abstraction level that can capture all the dice, and provide a unified representation of intent for placement and routing tools. A 3D floorplanner should work in the X, Y, and Z directions, and should have visibility into the top and bottom of each die. This helps optimize the placement of blocks, TSVs, and micro-bumps, and it shortens interconnect distances, thus improving performance and power. Ideally, a 3D floorplan has to be thermal-aware to avoid thermal hotspots and take mechanical stress into consideration. Thermal awareness will also help users determine the optimal placement of die into stacks

3D implementation

Synthesis, placement, and routing for 3D-ICs brings forth a number of new considerations. For example, there are new layout rules that may be driven by features on adjacent die. The back-side redistribution layer (RDL) is a new layout layer. And given their size, TSVs themselves are a significant new layout feature. An implementation system that supports 3D-ICs must be made “double-sided aware,” taking into account both the top and bottom of each die. This may call for a new modeling and database infrastructure, TSV-specific tools, and support for a variety of stacking styles.

With 3D-IC placement, optimization, and routing, it is important to build power, clock, and thermal considerations into the implementation solution. Analog implementation environments also need to add support for 3D-ICs. Examples of useful capabilities include multi-chip visualization with background views; support for bump, TSV, and reverse-side routing; and connectivity extraction maintained through TSV connections.

Throughout the design convergence process, design intent must be maintained and checked, and the necessary abstraction techniques must be applied for proper implementation and analysis.

3D extraction and analysis

If extraction and analysis wasn’t challenging enough in a 32nm 2D scenario, design convergence will be even more complicated with 3D-ICs. Existing extraction and analysis tools must consider RLC parasitics for TSVs, micro-bumps, and interposer routing, and they must be made 3D-aware. Timing, signal integrity, power, and thermal gradients must be analyzed across multiple die and take packaging into consideration.

Signoff raises new questions with 3D-IC stacks. When is the right time to sign off, and what are the appropriate signoff points? Can design rule checking (DRC) and layout-versus-schematics (LVS) run on the entire stack? Should and can timing be verified for the entire stack? Is there any crosstalk between die? Finally, electromagnetic interference (EMI) is a potential concern for 3D–ICs and a consideration for the analysis tools.