3D IC Design page 3
Last but not least, design for test (DFT) for 3D-ICs is even more critical than for 2D ICs. While wire-bonded systems-in-package (SiPs) may have a few hundred interconnects, 3D-ICs may have thousands if not tens of thousands of interconnects. Even a single defective TSV can render an entire stack unusable. If individual TSVs have 99.9% yield, at least one defective TSV can be expected in a stack of 1,000 TSVs.
A sound test methodology for 3D-ICs is necessary for IC designers to have the confidence to design them and to enable per-bond, mid-bond, post-bond, and post-package (final) testing. Fortunately, solutions are starting to emerge (see Figure 6). 3D-IC testing can leverage a large body of technology and experience with modular SoC testing by using DFT wrappers and extending them to 3D testing. In the SoC world, modular testing is made possible by DFT wrappers such as the IEEE 1149.1 boundary scan standard and the IEEE 1500 embedded core test standard. For 3D-IC testing, these wrappers need to be enhanced with 3D-specific extensions such as the following:
Additional probe pads for pre-bond testing
- Test “turnarounds” that start and finish the test access points at the bottom side of each die
- Test “elevators” that propagate test data vertically through the stack
Figure 6: The imec-Cadence implementation of a 3D-IC DFT architecture within the Cadence Encounter environment (source: imec)
To provide test generation, the wrappers should support both the internal testing of each die as well as all the inter-die interconnect logic and TSVs. In addition to the traditional fault models used for digital testing (stuck-at, transition, stuck-open, bridge faults), 3D-ICs require specific interconnect fault models to test the TSVs and micro-bumps. The test architecture described here was refined through collaboration between Cadence and the Belgian research institute imec.
What this means for a designer
In addition to expanding EDA tools to be 3D-aware, designers have to start thinking in 3D as well. For system architects, 3D-IC architectures open up a new world of possibilities. At the same time they also introduce a lot of moving parts that architects must be aware of while doing system planning. There are many considerations for deciding on the most optimized and cost-effective architecture. System architects must factor in new technical challenges and costs associated with the 3D-IC ecosystem to make it all work together.
If the life of IC designers was hard enough in 2D, 3D-ICs will not make it any easier. Designers need to understand the new technical challenges with 3D-ICs—thermal, test, crosstalk, etc.—and account for these in their individual die, but that alone is not sufficient. Before designers can sign off their die, they need to interact with whoever designed the die on top of their die, as well as the IC designer for the bottom die/package. Handoffs between the same company’s designers are difficult enough, and 3D-IC die handoffs could be between different companies or participants in the ecosystem.
EDA tools can help minimize some of those interactions by providing a common platform, yet the overall design task will get challenging where dies are coming from different places and are implemented in different environments. A proper handoff point must be agreed upon by the industry to make it easier for IC designers to exchange design data. In addition, designers need to expand their thinking to the system context. Knowing just their die and what it is supposed to do will not be sufficient. Having a complete picture and understanding of the system(s) their die can potentially go into will become one of the differentiating factors for their product.
3D-ICs with TSVs are an increasingly attractive option, and they need “3D-aware” design tool support. Isolated point tools won’t result in optimized, cost-effective solutions that take full advantage of the potential benefits of 3D-ICs. What’s needed is a comprehensive end-to-end solution that serves digital, analog, and package design teams.