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Rather than using bumps to interconnect between substrates, why not use an ...
The Fast Track to 3D-IC Testing
Chris Allsup and Adam Cron, Synopsys, Inc. Chen-An Chen and Yee-Wen Chen, Industrial Technology Research Institute.
1/16/2012 12:13 PM EST
Design for 3D Test
Although DFT standards for 3D-IC testing are still evolving (IEEE Std P1838 is the proposed architecture standard for test access), it is possible today to implement 3D DFT architectures based on existing standards and 3D test flows based on existing test automation solutions and their extensions. At ITRI, we have developed a practical DFT architecture for 3D-IC testing that combines elements of IEEE Std 1149.1 and core-wrapping for test access, a flexible user-defined instruction (UDI) set, and pin-limited scan compression. ITRI’s proposed DFT/ATPG implementation flow uses Synopsys’ synthesis-based test solution, which is comprised of DFTMAX compression and TetraMAX ATPG [9].
Some of the KGD test access issues discussed previously can be avoided by utilizing a small number of dedicated probe pads for pre-bond testing. Although there is an area overhead penalty for inserting “sacrificial” probe pads that will only be used for testing, ITRI believes the cost benefits of having KGD before stacking outweigh the negatives. For pre-bond test access, all dies use the IEEE Std 1149.1 serial interface for both test instructions and test data; the six test signals are the JTAG ports (TCK, TMS, TDI, TDO, and TRSTN) plus a ShiftEn, which affords some additional DFT flexibility. Our DFT architecture combines the boundary scan registers and die wrappers with the internal scan chains in the compression logic synthesized by DFTMAX (Figure 3). Utilizing the pin-limited test feature in the product to compress the ATPG patterns is key to reducing test application time and lowering the cost of 3D-IC testing.
For post-bond test access to dies further up the stack, the test interfaces on each die are daisy-chained up the stack and back down again (Figure 4). Generic boundary scan instructions as well as user-defined instructions control the logic that selects test data going up or coming down the stack, and determine the different kinds of scan tests that are performed. The architecture supports interconnect testing between neighboring dies in the stack, and has the flexibility to test multiple dies in the stack simultaneously.
Figure 4: ITRI's test access mechanism provides a flexible and convenient method to control test data
ITRI’s test implementation flow (Figure 5) requires configuring the scan chains for wrapper and boundary scan insertion using DFTMAX, then specifying how these chains will be incorporated into the compressor/decompressor (CODEC) logic. When the CODECs are synthesized, DFTMAX generates the test protocol file. TetraMAX ATPG then processes it to generate the test patterns for the various test modes, such as INTEST, EXTEST, SERIALIZE, MBIST, etc. The KGD patterns for the pre-bond tests are subsequently translated into stack-level patterns for the post-bond tests.
Figure 5: 3D-IC test pattern generation flow using Synopsys' synthesis-based test solution
There are additional capabilities in the Synopsys test solution which provide access to embedded test and debug features via the IEEE Std 1149.1 Test Access Port (TAP) that are especially beneficial for 3D-IC testing and diagnosis. One example is the DesignWare Self-Test and Repair (STAR) Memory System, which enables embedded test and repair of memories and works in conjunction with DFTMAX. The system receives instructions via the JTAG TAP and uses IEEE Std 1500 interfaces to provide the necessary test access and isolation for memories that reside on all the dies in the stack, including Wide I/O mobile memory with TSV interconnects. Another example is self-test of high-speed SERDES I/Os, for which the DesignWare IP has built-in TAP access to characterization and debug resources.
Both of these capabilities seem to be compatible with IEEE Std P1687, the proposed instrumentation standard, and are examples of the type of instrument access mechanisms that are critical for successful 3D-IC product certification and deployment. In addition to the standards we have discussed, Synopsys’ test solution employs STIL (IEEE Std 1450.x) and CTL (IEEE Std 1450.6) as mainstream interfaces to other systems in the electronics design and manufacturing industry, and as means to enable 2.5D- and 3D-IC testing.
Conclusion
Although advances in manufacturing and packaging technologies have brought 2.5D systems within reach, high-volume production of 3D-IC integration is still a few years away due to a number of technical and business hurdles that have yet to be overcome, some of which concern test. Test automation is a critical part of 3D-IC requirements, and will continue to evolve to meet the future needs of the semiconductor industry as experience grows and standards for testing 3D-ICs converge. Despite the dearth of ratified standards, organizations like ITRI are already using Synopsys’ synthesis-based test solution to rapidly develop their 3D-IC test flows. Advanced capabilities proven to be effective at testing today’s most complex 2D systems-on-chip—slack-based transition delay ATPG, power-aware and power domain-based testing, pin-limited compression, and embedded self-test for debug and diagnosis—will be essential for achieving the quality and cost requirements of tomorrow’s 3D-ICs.
References
[1] Sunohara, M., Tokunaga, T., Kurihara, T., Higashi, M., “Silicon Interposer with TSVs (Through Silicon Vias) and Fine Multilayer Wiring,” Electronic Components and Technology Conference, 2008.
[2] Chen, K.N., Tan, C.S., “Integration Schemes and Enabling Technologies for Three-Dimensional Integrated Circuits,” IET Computers & Digital Techniques, Volume 5, Issue 3, 2011, Pages 160–168.
[3] Taouil, M., Hamdioui, S., Beenakker, K., Marinissen, E.J., “Test Cost Analysis for 3D Die-to-Wafer Stacking,” 19th IEEE Asian Test Symposium (ATS), 2010, Pages 435–441.
[4] Bottoms, W.R., “Test Challenges for 3D Integration (an invited paper for CICC 2011),” IEEE Custom Integrated Circuits Conference (CICC), 2011, Pages 1–8.
[5] Marinissen, E.J., Daenen, T., Dupas, L., Van Dievel, M., Hanaway, P., Kiesewetter, J., Smith, K., Strid, E., Thärigen, T., “Wafer Probing on Fine-Pitch Micro Micro-Bumps for 2.5D- and 3D-SICs,” IEEE South-West Test Workshop–San Diego, California, June 2011.
[6] Sayil, S., “Optical Contactless Probing: An All-Silicon, Fully Optical Approach,” IEEE Design & Test of Computers, Volume 23, Issue 2, 2006, Pages 138–146.
[7] Zoschke, K., Wegner, M., Wilke, M., Jurgensen, N., Lopper, C., Kuna, I., Glaw, V., Roder, J., Wunsch, O., Wolf, M. J., Ehrmann, O., Reichl, H., “Evaluation of Thin Wafer Processing Using a Temporary Wafer Handling System as Key Technology for 3D System Integration,” 60th Proceedings of the Electronic Components and Technology Conference (ECTC), 2010, Pages 1385–1392.
[8] Chen, Y., Kursun, E., Motschman, D., Johnson, C., Xie Y., “Analysis and Mitigation of Lateral Thermal Blockage Effect of Through-Silicon-Via in 3D IC Designs,” Low Power Electronics and Design (ISLPED), 2011, Pages 397–402.
[9] DFTMAXTM Compression User Guide, Version F-2011.09, September, 2011; TetraMAX® ATPG User Guide, Version F-2011.09-SP1, October, 2011, Synopsys, Inc.
Chen-An Chen, deputy engineer for the design automation technology division at ITRI, has been with the company for 3 years. He earned a MSEE degree from National Changhua University of Education. His research interests include design-for-testability, low-power design and 3D-SIC testing exploration. He is currently a member of IEEE Std P1838.
Yee-Wen Chen is a technical deputy manager for the design automation technology division at ITRI. She earned a MSEE degree from National Taiwan University. She has more than 10 years experience in chip design and IC design flow.
Chris Allsup, marketing manager in Synopsys’ synthesis and test group, has more than 20 years combined experience in IC design, field applications, sales, and marketing. He earned a BSEE degree from UC San Diego and an MBA degree from Santa Clara University. Chris has authored numerous articles and papers on design and test.
Adam Cron, principal engineer at Synopsys, is part of the Test Automation Corporate Applications Engineering team and has been with the company for 14 years. A Syracuse University graduate, Adam has worked in test-related fields at Motorola and Texas Instruments for a total of 25 years in the industry. Adam has worked on many IEEE standards efforts, is currently vice-chair of IEEE Std P1838, and is an IEEE Golden Core recipient.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
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Although DFT standards for 3D-IC testing are still evolving (IEEE Std P1838 is the proposed architecture standard for test access), it is possible today to implement 3D DFT architectures based on existing standards and 3D test flows based on existing test automation solutions and their extensions. At ITRI, we have developed a practical DFT architecture for 3D-IC testing that combines elements of IEEE Std 1149.1 and core-wrapping for test access, a flexible user-defined instruction (UDI) set, and pin-limited scan compression. ITRI’s proposed DFT/ATPG implementation flow uses Synopsys’ synthesis-based test solution, which is comprised of DFTMAX compression and TetraMAX ATPG [9].
Some of the KGD test access issues discussed previously can be avoided by utilizing a small number of dedicated probe pads for pre-bond testing. Although there is an area overhead penalty for inserting “sacrificial” probe pads that will only be used for testing, ITRI believes the cost benefits of having KGD before stacking outweigh the negatives. For pre-bond test access, all dies use the IEEE Std 1149.1 serial interface for both test instructions and test data; the six test signals are the JTAG ports (TCK, TMS, TDI, TDO, and TRSTN) plus a ShiftEn, which affords some additional DFT flexibility. Our DFT architecture combines the boundary scan registers and die wrappers with the internal scan chains in the compression logic synthesized by DFTMAX (Figure 3). Utilizing the pin-limited test feature in the product to compress the ATPG patterns is key to reducing test application time and lowering the cost of 3D-IC testing.
Figure 3: ITRI's architecture uses the pin-limited test feature in DFTMAX to lower the cost of 3D-IC testing.
For post-bond test access to dies further up the stack, the test interfaces on each die are daisy-chained up the stack and back down again (Figure 4). Generic boundary scan instructions as well as user-defined instructions control the logic that selects test data going up or coming down the stack, and determine the different kinds of scan tests that are performed. The architecture supports interconnect testing between neighboring dies in the stack, and has the flexibility to test multiple dies in the stack simultaneously.
Figure 4: ITRI's test access mechanism provides a flexible and convenient method to control test data
ITRI’s test implementation flow (Figure 5) requires configuring the scan chains for wrapper and boundary scan insertion using DFTMAX, then specifying how these chains will be incorporated into the compressor/decompressor (CODEC) logic. When the CODECs are synthesized, DFTMAX generates the test protocol file. TetraMAX ATPG then processes it to generate the test patterns for the various test modes, such as INTEST, EXTEST, SERIALIZE, MBIST, etc. The KGD patterns for the pre-bond tests are subsequently translated into stack-level patterns for the post-bond tests.
Figure 5: 3D-IC test pattern generation flow using Synopsys' synthesis-based test solution
There are additional capabilities in the Synopsys test solution which provide access to embedded test and debug features via the IEEE Std 1149.1 Test Access Port (TAP) that are especially beneficial for 3D-IC testing and diagnosis. One example is the DesignWare Self-Test and Repair (STAR) Memory System, which enables embedded test and repair of memories and works in conjunction with DFTMAX. The system receives instructions via the JTAG TAP and uses IEEE Std 1500 interfaces to provide the necessary test access and isolation for memories that reside on all the dies in the stack, including Wide I/O mobile memory with TSV interconnects. Another example is self-test of high-speed SERDES I/Os, for which the DesignWare IP has built-in TAP access to characterization and debug resources.
Both of these capabilities seem to be compatible with IEEE Std P1687, the proposed instrumentation standard, and are examples of the type of instrument access mechanisms that are critical for successful 3D-IC product certification and deployment. In addition to the standards we have discussed, Synopsys’ test solution employs STIL (IEEE Std 1450.x) and CTL (IEEE Std 1450.6) as mainstream interfaces to other systems in the electronics design and manufacturing industry, and as means to enable 2.5D- and 3D-IC testing.
Conclusion
Although advances in manufacturing and packaging technologies have brought 2.5D systems within reach, high-volume production of 3D-IC integration is still a few years away due to a number of technical and business hurdles that have yet to be overcome, some of which concern test. Test automation is a critical part of 3D-IC requirements, and will continue to evolve to meet the future needs of the semiconductor industry as experience grows and standards for testing 3D-ICs converge. Despite the dearth of ratified standards, organizations like ITRI are already using Synopsys’ synthesis-based test solution to rapidly develop their 3D-IC test flows. Advanced capabilities proven to be effective at testing today’s most complex 2D systems-on-chip—slack-based transition delay ATPG, power-aware and power domain-based testing, pin-limited compression, and embedded self-test for debug and diagnosis—will be essential for achieving the quality and cost requirements of tomorrow’s 3D-ICs.
References
[1] Sunohara, M., Tokunaga, T., Kurihara, T., Higashi, M., “Silicon Interposer with TSVs (Through Silicon Vias) and Fine Multilayer Wiring,” Electronic Components and Technology Conference, 2008.
[2] Chen, K.N., Tan, C.S., “Integration Schemes and Enabling Technologies for Three-Dimensional Integrated Circuits,” IET Computers & Digital Techniques, Volume 5, Issue 3, 2011, Pages 160–168.
[3] Taouil, M., Hamdioui, S., Beenakker, K., Marinissen, E.J., “Test Cost Analysis for 3D Die-to-Wafer Stacking,” 19th IEEE Asian Test Symposium (ATS), 2010, Pages 435–441.
[4] Bottoms, W.R., “Test Challenges for 3D Integration (an invited paper for CICC 2011),” IEEE Custom Integrated Circuits Conference (CICC), 2011, Pages 1–8.
[5] Marinissen, E.J., Daenen, T., Dupas, L., Van Dievel, M., Hanaway, P., Kiesewetter, J., Smith, K., Strid, E., Thärigen, T., “Wafer Probing on Fine-Pitch Micro Micro-Bumps for 2.5D- and 3D-SICs,” IEEE South-West Test Workshop–San Diego, California, June 2011.
[6] Sayil, S., “Optical Contactless Probing: An All-Silicon, Fully Optical Approach,” IEEE Design & Test of Computers, Volume 23, Issue 2, 2006, Pages 138–146.
[7] Zoschke, K., Wegner, M., Wilke, M., Jurgensen, N., Lopper, C., Kuna, I., Glaw, V., Roder, J., Wunsch, O., Wolf, M. J., Ehrmann, O., Reichl, H., “Evaluation of Thin Wafer Processing Using a Temporary Wafer Handling System as Key Technology for 3D System Integration,” 60th Proceedings of the Electronic Components and Technology Conference (ECTC), 2010, Pages 1385–1392.
[8] Chen, Y., Kursun, E., Motschman, D., Johnson, C., Xie Y., “Analysis and Mitigation of Lateral Thermal Blockage Effect of Through-Silicon-Via in 3D IC Designs,” Low Power Electronics and Design (ISLPED), 2011, Pages 397–402.
[9] DFTMAXTM Compression User Guide, Version F-2011.09, September, 2011; TetraMAX® ATPG User Guide, Version F-2011.09-SP1, October, 2011, Synopsys, Inc.
Chen-An Chen, deputy engineer for the design automation technology division at ITRI, has been with the company for 3 years. He earned a MSEE degree from National Changhua University of Education. His research interests include design-for-testability, low-power design and 3D-SIC testing exploration. He is currently a member of IEEE Std P1838.
Yee-Wen Chen is a technical deputy manager for the design automation technology division at ITRI. She earned a MSEE degree from National Taiwan University. She has more than 10 years experience in chip design and IC design flow.
Chris Allsup, marketing manager in Synopsys’ synthesis and test group, has more than 20 years combined experience in IC design, field applications, sales, and marketing. He earned a BSEE degree from UC San Diego and an MBA degree from Santa Clara University. Chris has authored numerous articles and papers on design and test.
Adam Cron, principal engineer at Synopsys, is part of the Test Automation Corporate Applications Engineering team and has been with the company for 14 years. A Syracuse University graduate, Adam has worked in test-related fields at Motorola and Texas Instruments for a total of 25 years in the industry. Adam has worked on many IEEE standards efforts, is currently vice-chair of IEEE Std P1838, and is an IEEE Golden Core recipient.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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Upstream swimmer
1/17/2012 12:24 PM EST
Rather than using bumps to interconnect between substrates, why not use an anisotropic conductive film (ACF)? This would allow testing and rejection of any defective chips.
- Peter C. Salmon
peter@petersalmon.com
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