Calibre PERC: Preventing Electrical Overstress Failures

Circuit reliability is a challenge facing all IC designers. With target applications ranging from RFID tags to controllers for the automotive and aircraft markets, it is crucial that designers understand and address the sources of possible circuit failure to ensure a robust design and reliable operation. Two essential factors to be considered include the desired lifetime of the circuit and the type of environment(s) in which the circuit will operate. That understanding will identify the external temperature, electrical, magnetic, and mechanical stresses to which the circuit will be susceptible.

With that knowledge, the designer can develop a strategy for circuit reliability that includes design, simulation, and verification techniques to ensure the circuit can withstand these stresses. Reliability verification can be a powerful part of this strategy; using techniques such as programmable electrical rule checking (PERC) and automated voltage propagation, designers can now address the circuit verification challenges while reducing simulation requirements. This article presents an example of how a circuit reliability verification tool (in this case, Calibre® PERC™) can be deployed to prevent electrical circuit failure due to electrical overstress (EOS), and improve overall circuit reliability.

Traditional Uses for Circuit Reliability Checking
A common application of circuit reliability checking is to ensure that a design has adequate protection against electrostatic discharge (ESD) events [1]. An ESD failure is usually due to an external event, such as a manufacturing step, probe/pin, or person inducing a large voltage to the circuit, which causes a gate-oxide breakdown or other circuit failures due to the circuit’s response to this large voltage. Predicting the exact path an ESD event will traverse through your circuit is nearly impossible, so the industry has developed techniques to mitigate the asynchronous introduction of large voltage spikes. Special circuits (clamping devices) are implemented around the I/O pads of the circuit to dissipate large amounts of charge before they reach the sensitive internal circuitry of the core IC. Calibre PERC can be used to ensure that these ESD structures and devices have been implemented appropriately by performing topological verification. It can also be used to validate electrical compliance by performing resistance and current density measurements to ensure that the wiring of these devices is robust enough to support the large currents that can be induced.

New Applications for Circuit Reliability Checking
In contrast to external ESD events, this article focuses on improving reliability by eliminating an internal design flaw that could result in EOS. Our EOS example presents a simple, yet sinister problem involving a sensitive thin-oxide transistor connected to a high voltage. This construction can lead to medium/long-term electrical failure as the gate oxide breaks down over time. While this can happen with any process node or technology, as the industry migrates to 20nm (with 14nm design starts ~1 year away), gate oxides are becoming thinner and thinner, and hence are becoming even more vulnerable to EOS issues.

Compounding this issue, it is now routine for modern designs to have multiple power domains. Analog, logic, memory, and RF blocks coexist on a single IC and utilize different power sources (Vdd), making recognition of the problematic construction extremely challenging. In our example, high voltage is not really even that “high” (i.e., we are not talking about >50V voltage sources). In this case, a 5V Vdd connected to a 1.5V device would be enough to incur circuit failure.

EOS Example
Figure 1 shows sensitive thin-oxide transistors that are connected to Vdd2 instead of Vdd. If Vdd2 is a higher voltage than Vdd, then this circuit will contain an EOS issue and lead to circuit failure over time. This is a simple example with a simple remedy, but demonstrates how difficult it can be to identify these issues. To start with, this circuit is correct at the block level, with all of the blocks also correct individually. However, when they are connected to the top-level, usually after place and route (P&R), the voltage issue arises.


Figure 1: Thin-oxide transistor connected to Vdd2 at “top-level”

Using traditional methods, the designer has several options to detect such a problem, but each method has limitations, and cannot guarantee correct circuit performance in all cases:

1. Circuit Simulation: Transistor-level circuit simulation is normally considered to be the most accurate and thorough mechanism for addressing electrical issues, and one would assume that circuit simulation could be used to identify the problem. In this case, however, there are several shortcomings that prevent simulation from being successful. The first issue is that this is not a block-level problem, but a full-chip problem. In a typical modern circuit, data size would prevent circuit simulation from completing this task in any reasonable amount of time. Second, even if the circuit can be simulated at the full chip level, it may not find the problem because the problem is manifested as circuit degradation and failure over time. This circuit will typically fail days, weeks, or months after it is deployed in the field. Such a time dependency is not factored into most circuit simulations, or the device models built to support them.
2. Layout versus Schematic (LVS) comparison: LVS checking compares the schematic (logical) versus layout (physical representation) of the circuitry. For this example, if the layout matches Figure 1, but the schematic is correct, then LVS would identify an error and the designer could use that information to fix the circuit. However, if the schematic matches Figure 1, and the layout matches the schematic, then LVS will confirm that the schematic matches the layout, and the circuit error propagates downstream, probably to tape-out.
3. Other Tools and Techniques: Designers often have additional internal tools and techniques at their disposal that include design reviews, scripts, etc. These techniques can be error-prone and tedious. Also, given that this is a full-chip problem, these other techniques must be employed on large data sets with sophisticated hierarchies. It is unlikely that internal solutions can provide a reliable and robust methodology.

Fortunately, this type of problem can now be easily addressed with a new class of circuit reliability tools, such as Calibre PERC, that can start with topological recognition (meaning it can identify certain types of circuits, their connections, parameters, etc.), then compare all of those against an electrical constraint. While the nature of ESD problems differs from the EOS example we discuss here, users familiar with the use of Calibre PERC for ESD can easily apply the same methodology for EOS issues.

The procedure for this type of check consists of the following steps:

1. Identify all thin-oxide transistors. (In this example, recognize all of the *_thinOx devices),
2. For each device: identify the power supply to which it is connected,
3. Flag as an error any device that is connected to a power supply other than Vdd.

This operation is a topological check that can operate hierarchically, and is therefore very fast on either schematic or post-layout data, and completely accurate. It does not require designers to do anything differently in their design flow, so it does not disrupt either workflows or schedules.

Improved Flow with Voltage Propagation
The typical reaction to the previous example is that this check is quite powerful, but limited to devices that are connected explicitly to supply voltages, hence it only addresses a subset of devices that are vulnerable to electrical failure. To achieve completeness, the designer is faced with a dilemma: make voltage assignments manually, or interface to a circuit simulator for accurate characterization.  You will recognize that these are the same choices that we faced at the start of this problem.

To address this limitation, more advanced circuit reliability tools include their own voltage propagation capability, so they can deliver a complete, automated solution. Given the input voltages and user-defined rules as to how voltages should change at different points in the device, Calibre PERC can quickly make voltage assignments to every net/pin in the design (Figure 2). The designer can then utilize the check mentioned above for all devices, and achieve the accuracy and completeness necessary to ensure a robust design.
 

Figure 2: Calibre PERC can assign voltages to every node in the design to ensure complete checking, even for nodes not directly connected to supply rails.

Conclusion
For several decades, IC designers have benefitted from comprehensive methodologies to determine whether a circuit can be manufactured in modern processes. These methodologies revolve around designs being “DRC-clean,” which ensures that they are robust from a manufacturing perspective. Verification methods for electrical reliability have lagged behind—detecting the common sources of electrical failures was a bit of a black art, relying on internal methods, scripting, manual checking, and individual expertise. New commercial reliability tools such as Calibre PERC can now deliver fast, comprehensive and accurate verification that catches and corrects real circuit errors before the design goes to manufacturing.

References
[1] “Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes,” TSMC Open Innovation Platform Ecosystem Forum, 2011. http://www.tsmc.com/english/24papers-21-Mentor.htm

Author:
Carey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 14 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at carey_robertson@mentor.com.

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