Today’s complex ASICs often leverage open-market IP to take advantage of reuse of standard functional blocks, and thereby improve time to market and development efficiency. However, the integration of that third-party IP, if done poorly, can lead to painful cost overruns and schedule delays. To ensure proper IP core integration, Open-Silicon has developed a detailed and comprehensive process involving close collaboration with IP partners and the SoC design team. This article will illustrate this process by showing how Open-Silicon and Kilopass worked together on a recent project to ensure success.
At the highest level, Open-Silicon employs a four-step process to ensure that the IP included in its design will achieve first-time silicon success. These steps include IP selection, IP procurement, IP qualification and IP integration. Each of these steps is detailed below.IP selection
In this recent design, Open-Silicon chose a high performance process from one of the leading foundries. The Kilopass anti-fuse OTP hard macro (GDSII) non-volatile memory (NVM) is widely available at most foundry process nodes and was also available in this target process. As for IP features, the design required that the NVM be field programmable, provide 8Kb of storage capacity, and be tamper-resistant. In the design, the memory will provide secure storage for analog-to-digital (A/D) converter trim data, Media Access Control (MAC) address, and cryptographic keys. Another advantage of embedding anti-fuse OTP NVM IP is the protection it provides against inexpensive and simple passive tampering as well as elaborate and costly invasive tampering.
During IP selection, the Open-Silicon design team had several tradeoffs to consider when choosing the right anti-fuse OTP NVM. The first was determining whether to use an on-chip charge pump for programming the memory or to use an external programming voltage. On-chip charge pumps are a standard Kilopass option for the XPM 8Kb OTP. Because a third-party certification agency required the design to be programmable with on-chip resources, the on-chip charge pump 8Kb was chosen.
Once it was determined to use the 8kb XPM OTP, the Open-Silicon team had to select interface bit-width for accessing the NVM. Each interface alternative has its own speed, power, and timing considerations. The team selected the 8-bit parallel alternative as it had the least impact on test time. IP procurement
Open-Silicon’s technical IP procurement process has been fine-tuned from the integration of a wide variety of IP cores into hundreds of ASIC designs. This process is something that continues to get refined as new technologies come to market. Some of the important points that provide insight and confidence into a new IP vendor or a new IP product include the following:
- Verifying deliverables the IP vendor supplies to ensure they meet industry norms and comply with Open-Silicon’s EDA flow and methodology.
- Determining foundries and process nodes where the IP block has been qualified.
- Determining the level and extent of technical support that will accompany the IP.
- Determining what special processes, if any, will be needed to manage IP functional or integration risk during device design.
The result of this evaluation is a risk/maturity assessment. For the Kilopass XPM 8Kb OTP NVM, key factors were that the OTP NVM IP block was silicon-proven at the target foundry and process node, that it came with complete technical deliverables (.GDSII module, GDSII Frame, LEF/Antenna LEF (Layout Extraction Format) and LVS (layout-versus-schematic) netlists, Verilog models, .lib and .db models, and that it included robust design documentation including design integration guidelines, system design guidelines, data sheet, etc.—all those elements required for a successful tape out.IP qualification
The objective of the IP Qualification is to do the necessary checks on the incoming IP as early as possible, long before the design team integrates it in the ASIC. This approach provides significant lead-time for the IP vendor to fix any issues upfront, which might show up in the ASIC tape-out phase of the project. The cost to fix any error in IP increases exponentially as it moves forward through the various ASIC design phases and hence early IP quality assurance is really important.
During IP qualification, Open-Silicon performs quality assurance, which involves various front-end and back-end checks. The team checks that all deliverables supplied by an IP vendor will ensure the successful integration of the IP in the ASIC. For example, automated IP incoming quality control (IQC) programs determine if the GDSII is in correct format and verifies that the IP has no physical design errors when cross-checked with the exact PDK version of the technology used in the ASIC. In addition, various IP views are compared to ensure consistency. For example, verifying that pins modeled in Verilog views are present in the LEF/LIB/GDSII views as well. IP integration
IP integration at Open-Silicon is a two-fold process. It begins during the floor planning stage when the team determines where to place the XPM NVM block as well as all the other blocks in the design. This also involves ensuring the IP’s required power supply connectivity and intercommunication is taken into consideration from the die/packaging perspective. Kilopass, as well as other IP vendors, publishes an integration guideline that specifies where the memory must be placed in the larger layout. For the Kilopass XPM, the guideline calls for placing the block in a corner. In addition, guidelines specify routing of the power buses, minimum width of the power buses, etc.
The IP integration team creates a design-specific custom checklist of all the IP blocks and their respective integration requirements. One of the sign-off items at key design milestones and before final tape out is to ensure that IP integration checks have been successfully completed. A final review with the IP vendor is performed after IP merge. In this example, the dropping in of the Kilopass XPM block hard macro, is complete and the entire design GDSII is ready. In summary
With the increasing amount of third-party IP finding it way onto today's complex system-on-chip designs, it is paramount that designers build a large and expanding knowledge base incorporating lessons learned into checklists, automated IC analysis programs, and internal and collaborative processes. This includes the accumulated experience from hundreds of designs containing a broad range of IP blocks. This knowledge base is combined with the experience of the individual IP vendors to bring the lowest possible risk to each design. This design example illustrated the various stages of using open market IP, and many of the steps taking to ensure silicon success. About the authors
Mohit Gupta, Open-Silicon
Mohit Gupta is an IP manager with Open-Silicon, and is responsible for managing the IP for various networking, telecom, storage and consumer application programs. Prior to joining Open-Silicon, Mohit led teams at Infineon Technologies and STMicroelectronics where he was responsible for IP circuit design, layout design, characterization and quality assurance of IP. Gupta holds a BE Degree in EEC from Thapar University, India and an MS degree in Microelectronics from the Birla Institute of Science and Technology, Pilani, India. He also participated in the Executive Program in International Business Management from Indian Institute of Management, Calcutta, India.
Bernd Stamme, Kilopass Technology Inc.
Bernd Stamme is director for Marketing and Applications at Kilopass Technology. He has more than 15 years of experience in the IP and semiconductor industry. Prior to Kilopass, he was the director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets. Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.
If you found this article to be of interest, visit EDA Designline
where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here
to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).