2. RTL simulation and realistic activity data
Next, we simulated
the design using a SystemVerilog testbench and we logged the switching
activity on key points of the design. A number of formats are supported
for activity including VCD, TCF, and SAIF. TCF (toggle count format – a
simple Cadence-specific format) and SAIF (switching activity interchange
format – standardized as part of IEEE-1801) are both averaging formats.
They count the number of toggles on a given signal in a certain time
window, and give relatively compact data files.
VCD (value change
dump) is a common waveform format that stores every value change at the
signal level. It can give greater accuracy to explore peaks of activity,
but can quickly create huge data files. Many designers employ
strategies that start with an averaging format to get a sense of average
power in each operating mode, and then switch to VCD on short runs only
to explore power peaks.
For the purposes of this exercise, we used
SAIF. The testbench exercised the design for various modes with
different activity levels in both MACs, including modes with both MACs
fully active and both idle.
We captured windows of the activity data
in full-run mode and the all-idle mode. These are shown in Table 2. We
can immediately see two things. First, our initial full-run mode
estimate was wildly off, illustrating the need for activity data for any
hope of accuracy. Second, we see that idle power is almost 60% of the
power when both MACs are running, which seems much too high. Next, we
will explore techniques to address both dynamic and leakage power
Table 2: Estimate with Realistic Activity Data
3. MSV implementation
the next step, we separated each MAC into its own power domain, and
applied multi-supply voltage (MSV). We had deduced that the performance
bottleneck for the dual Ethernet MAC design was in the DMA processing,
rather than the MACs. Hence, we changed the supply voltage for each MAC
to 0.9V to optimize for power, and left the rest of the design at 1.08V
to preserve performance. MSV has little impact on verification at the
RTL stage – the timing effects of different voltages are only apparent
at the gate level, and there is no need to model insertion of level
shifters for RTL verification. We repeated power estimation and obtained
the results shown in Table 3.
Table 3: Estimate with MSV – Both MACs at 0.9V
estimate reveals a power reduction of approximately 30%, regardless of
mode. In the idle mode, while the MACs are inactive, we are still seeing
power at about 60% of the fully active mode. Obviously, clock gating
alone is not enough to reduce dynamic power in the design to the level
we’d expect. We need to apply more drastic measures.