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2012 will be the year of power, again
Brett Cline
4/25/2012 11:01 AM EDT
RTL Code Creation and Verification
Once the model representing the algorithm and architecture is functional and validated, architects and designers can use HLS to get an initial RTL code candidate implementation. Varying switches or directives on the HLS tool can give widely different RTL results depending on the project needs. For instance, the designer can choose to pipeline a design, unroll loops or use registers or memories for storage. All of the same implementation or micro-architecture decisions that a hardware designer would normally do can be done automatically with HLS. And, best of all, each micro-architecture will produce another candidate RTL implementation where real results can be measured.
What about power? A couple of interesting power-related things are happening at this point. First, as the HLS tool creates the RTL code, it should be doing so with best-known practices. These include design styles (micro-architecture) and coding styles that will produce consistently good area and power results, as well as:
The second interesting power related item is in the form of flow integration. The more sophisticated HLS tools also include full automation and data management systems that allow the users to quickly push several candidate RTL implementations downstream through RTL tools such as power estimation, logic synthesis, code analysis, simulation, and more. Using the automation system, architects and designers have access to the best-in-class RTL implementation and estimation tools without having to specifically be experts in using those tools. The results are then captured and presented to the user in an intuitive manner.
Obviously, at any point in the process, optimizations can be done at various levels and pushed back through the flow to understand the resulting QoR changes. This is critical to ultimately reaching the desired quality targets. With HLS, this can be done more quickly and across a wider variety of design tradeoffs - including power.
Summary
Every design team wants their design to use less power, especially if there are no other tradeoffs. Sometimes with better design techniques we can do just that. More often, there are tradeoffs that have to be made and, for power, that usually requires changes in the architecture to yield any significant improvements. High-level synthesis brings the ability to use real data to make smart architectural tradeoffs by allowing design teams to quickly get from a high-level algorithm to a real RTL description in less time than with a traditional hand-coded RTL flow. Utilizing the highly abstracted input models and HLS together allows designers to quickly access state-of-the-art RTL analysis and implementation tools better quantify the results of their decisions. With this flow and methodology it’s now possible to make better decisions and far earlier in the process.
French Critic Jean-Baptiste Alphonse Karr (1808-1890) once said, “the more things change, the more they stay the same.” Even though design methodologies are evolving with more and more users adopting SystemC and high-level synthesis, it looks like 2012 will be the year of power, again.
1. Power PC 970: http://en.wikipedia.org/wiki/PowerPC_970
About the author
Brett Cline is vice president of marketing and sales at Forte Design Systems. Before joining Forte in 1999, Cline was director of marketing at Summit Design, where he managed both the verification product line and marketing communications. Cline has also held positions in development, applications and technical marketing at Cadence Design Systems and General Electric. He holds a Bachelor of Science degree in Electrical Engineering from Northeastern University in Boston and serves on the Board of Directors of Provis Corporation in Minneapolis.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
Once the model representing the algorithm and architecture is functional and validated, architects and designers can use HLS to get an initial RTL code candidate implementation. Varying switches or directives on the HLS tool can give widely different RTL results depending on the project needs. For instance, the designer can choose to pipeline a design, unroll loops or use registers or memories for storage. All of the same implementation or micro-architecture decisions that a hardware designer would normally do can be done automatically with HLS. And, best of all, each micro-architecture will produce another candidate RTL implementation where real results can be measured.
What about power? A couple of interesting power-related things are happening at this point. First, as the HLS tool creates the RTL code, it should be doing so with best-known practices. These include design styles (micro-architecture) and coding styles that will produce consistently good area and power results, as well as:
- Using a consistent, high-quality RTL coding style that is known to be good for downstream RTL tools
- Maximizing the sharing of datapath components to reduce leakage
- Disabling memories when not in use
- Enabling multiple different memory architectures to minimize switching
- Etc.
The second interesting power related item is in the form of flow integration. The more sophisticated HLS tools also include full automation and data management systems that allow the users to quickly push several candidate RTL implementations downstream through RTL tools such as power estimation, logic synthesis, code analysis, simulation, and more. Using the automation system, architects and designers have access to the best-in-class RTL implementation and estimation tools without having to specifically be experts in using those tools. The results are then captured and presented to the user in an intuitive manner.
Obviously, at any point in the process, optimizations can be done at various levels and pushed back through the flow to understand the resulting QoR changes. This is critical to ultimately reaching the desired quality targets. With HLS, this can be done more quickly and across a wider variety of design tradeoffs - including power.
Summary
Every design team wants their design to use less power, especially if there are no other tradeoffs. Sometimes with better design techniques we can do just that. More often, there are tradeoffs that have to be made and, for power, that usually requires changes in the architecture to yield any significant improvements. High-level synthesis brings the ability to use real data to make smart architectural tradeoffs by allowing design teams to quickly get from a high-level algorithm to a real RTL description in less time than with a traditional hand-coded RTL flow. Utilizing the highly abstracted input models and HLS together allows designers to quickly access state-of-the-art RTL analysis and implementation tools better quantify the results of their decisions. With this flow and methodology it’s now possible to make better decisions and far earlier in the process.
French Critic Jean-Baptiste Alphonse Karr (1808-1890) once said, “the more things change, the more they stay the same.” Even though design methodologies are evolving with more and more users adopting SystemC and high-level synthesis, it looks like 2012 will be the year of power, again.
1. Power PC 970: http://en.wikipedia.org/wiki/PowerPC_970
About the author
Brett Cline is vice president of marketing and sales at Forte Design Systems. Before joining Forte in 1999, Cline was director of marketing at Summit Design, where he managed both the verification product line and marketing communications. Cline has also held positions in development, applications and technical marketing at Cadence Design Systems and General Electric. He holds a Bachelor of Science degree in Electrical Engineering from Northeastern University in Boston and serves on the Board of Directors of Provis Corporation in Minneapolis.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
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