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Book excerpt: Power integrity for I/O interfaces: with signal integrity/power integrity co-design Part 4
Vishram S. Pandit, Woong Hwan Ryu, Myoung Joon Choi
4/26/2012 10:27 AM EDT
From the Preface:
Power Integrity is becoming increasingly important in todays high-speed digital I/O systems. The cover of this book gives a high-level summary of its system impact. It shows an electronic system with a Printed Circut Board (PCB), a daughter card, and their layer stackup. A driver chip is mounted on the PCB and a receiver chip is mounted on the daughter card. The expanded view of the power grid of the driver chip is also shown. The receiver jitter impact is due to Power Delivery (PD) to signal coupling, and there are different coupling mechanisms. Self impedance response of the PDN at the driver chip shows a resonance in the mid-frequency range. The PD to signal coupling response at the driver chip follows the PDN self impedance response. The jitter at the receiver follows a similar signature at those frequencies when the transmission line effect is negligible. The PD to signal coupling at the package to PCB interface increases as the frequency goes higher. The channel response shows resonances at high frequencies, due to impedance discontinuities. The power to signal coupling noise can get amplified due to the channel effects and resonances. This, in turn, gets translated into jitter at the receiver at high frequencies. Referencing scheme, such as dual referencing, also causes the PD to signal coupling.
Intended audience for this book is Signal Integrity (SI) and Power Integrity (PI) Engineers (On-chip, package, and PCB designers). It can also be used by graduate students who want to pursue careers in these fields. Overall discussion level is beginner to intermediate; however, some advanced topics are also discussed. There may be different designers working on specific components, such as on-chip or package or PCB. However, this book presents power integrity design techniques along with power-to-signal coupling mechanisms at various stages in the system, such as chip level coupling and interconnect level coupling. This will give the component SI or PI engineers a perspective of system level impact of power integrity, and enable them to proactively design the system to avoid possible problem areas and also to identify the root-cause, in case of any system problems.
Chapter Listing
Chapter 1. Input Output Interface
Chapter 2. Electromagnetic Effects
Chapter 3. Power/ Ground and Signal Distribution Network
Chapter 4. Frequency Domain Analysis
Chapter 5. Time Domain Analysis
Chapter 6: Signal Integrity/ Power Integrity Interaction
Chapter 7: Signal Integrity/ Power Integrity Co-Analysis – Chapter being featured
Chapter 8: Measurements
The book can be purchased here.
Chapter 7: Signal/Power Integrity Interactions
As the Printed Circuit Board (PCB) interconnection density and channel data rate increasingly intensify, various 3D electromagnetic effects, crosstalk, and discontinuity- induced ISI represent an even more significant role for both signal channels and power distribution networks. In particular, noise coupling between signal trace and power delivery network constitutes a key issue and performance limiter for the high-speed I/O interface, which must be addressed appropriately. Understanding these combined signal integrity and power integrity issues in the era of gigahertz data rate requires advanced co-design methodology for signal integrity and power integrity analysis. In this chapter, we describe power/signal integrity interaction mechanism, including power noise coupling onto signal trace and noise amplified through signal resonance.
Part 1 included:
7.1 Background
7.2 Root Cause Analysis
7.3 SSO Coupling Mechanisms
7.4 Case Study 1: DDR2 800 Control Signals
Second segment included
7.5 Case Study 2: DDR2 667 Vref Bus
Third segment:
7.6 Referencing/Stitching/ Decoupling Effects – Single Ended Interface
7.7 Stitching Effects – Differential Results
Final segment:
7.8 EMI Trade-off
About the authors
Vishram S. Pandit is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing power delivery designs for high-speed interfaces. His focus areas include high-speed system power delivery, on-chip power delivery, and Signal/ Power Integrity co-design. Prior to Intel he worked at Hughes Network Systems on Electromagnetic Interference (EMI), Electromagnetic Compatibility (EMC), power integrity, and signal integrity technologies. He has received a B.E. (Instrumentation) from College of Engineering, Pune, India, an M.S. (Electrical Engineering) from University of Utah, USA, and an Advanced Certificate for Post-Master’s Study (Computer Science) from Johns Hopkins University, USA. He is a senior member of IEEE and a member of the CPMT Technical Committee on Electrical Design, Modeling and Simulation; and he serves as a technical program committee member for DesignCon. He was a recipient of the International Engineering Consortium’s paper awards for DesignCon 2008 and DesignCon 2009.
Woong Hwan Ryu is currently a Signal/Power Integrity Engineering Manager at Intel Corporation. He has been responsible for pre-silicon signal integrity and power integrity analysis for high speed interfaces. He received his Ph.D. degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST). Dr. Ryu holds an IEEE Senior Member status; he serves as a reviewer for several IEEE journals; and he serves as a technical program committee member and organizing committee member for DesignCon. He was a recipient of the International Engineering Consortium’s paper awards for DesignCon 2006 and DesignCon 2008. Dr. Ryu has authored and co-authored more than 80 technical publications in premier journals and international conferences, and holds three issued patents and has one patent pending.
Myoung Joon Choi is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing methodologies for high-speed interface simulation and analysis. His focus areas include high-speed system SI-PI co-simulation, on-chip signal and power integrity, and computational analysis of entire high-speed systems. Dr. Choi has received a Ph.D. and an M.S. from University of Illinois at Urbana-Champaign, Urbana, IL, USA, and a BS from Korea University, Seoul, Korea. He has authored and co-authored many technical publications in journals and conferences.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
Power Integrity is becoming increasingly important in todays high-speed digital I/O systems. The cover of this book gives a high-level summary of its system impact. It shows an electronic system with a Printed Circut Board (PCB), a daughter card, and their layer stackup. A driver chip is mounted on the PCB and a receiver chip is mounted on the daughter card. The expanded view of the power grid of the driver chip is also shown. The receiver jitter impact is due to Power Delivery (PD) to signal coupling, and there are different coupling mechanisms. Self impedance response of the PDN at the driver chip shows a resonance in the mid-frequency range. The PD to signal coupling response at the driver chip follows the PDN self impedance response. The jitter at the receiver follows a similar signature at those frequencies when the transmission line effect is negligible. The PD to signal coupling at the package to PCB interface increases as the frequency goes higher. The channel response shows resonances at high frequencies, due to impedance discontinuities. The power to signal coupling noise can get amplified due to the channel effects and resonances. This, in turn, gets translated into jitter at the receiver at high frequencies. Referencing scheme, such as dual referencing, also causes the PD to signal coupling.
Intended audience for this book is Signal Integrity (SI) and Power Integrity (PI) Engineers (On-chip, package, and PCB designers). It can also be used by graduate students who want to pursue careers in these fields. Overall discussion level is beginner to intermediate; however, some advanced topics are also discussed. There may be different designers working on specific components, such as on-chip or package or PCB. However, this book presents power integrity design techniques along with power-to-signal coupling mechanisms at various stages in the system, such as chip level coupling and interconnect level coupling. This will give the component SI or PI engineers a perspective of system level impact of power integrity, and enable them to proactively design the system to avoid possible problem areas and also to identify the root-cause, in case of any system problems.
Chapter ListingChapter 1. Input Output Interface
Chapter 2. Electromagnetic Effects
Chapter 3. Power/ Ground and Signal Distribution Network
Chapter 4. Frequency Domain Analysis
Chapter 5. Time Domain Analysis
Chapter 6: Signal Integrity/ Power Integrity Interaction
Chapter 7: Signal Integrity/ Power Integrity Co-Analysis – Chapter being featured
Chapter 8: Measurements
The book can be purchased here.
Chapter 7: Signal/Power Integrity Interactions
As the Printed Circuit Board (PCB) interconnection density and channel data rate increasingly intensify, various 3D electromagnetic effects, crosstalk, and discontinuity- induced ISI represent an even more significant role for both signal channels and power distribution networks. In particular, noise coupling between signal trace and power delivery network constitutes a key issue and performance limiter for the high-speed I/O interface, which must be addressed appropriately. Understanding these combined signal integrity and power integrity issues in the era of gigahertz data rate requires advanced co-design methodology for signal integrity and power integrity analysis. In this chapter, we describe power/signal integrity interaction mechanism, including power noise coupling onto signal trace and noise amplified through signal resonance.
Part 1 included:
7.1 Background
7.2 Root Cause Analysis
7.3 SSO Coupling Mechanisms
7.4 Case Study 1: DDR2 800 Control Signals
Second segment included
7.5 Case Study 2: DDR2 667 Vref Bus
Third segment:
7.6 Referencing/Stitching/ Decoupling Effects – Single Ended Interface
7.7 Stitching Effects – Differential Results
Final segment:
7.8 EMI Trade-off
About the authors
Vishram S. Pandit is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing power delivery designs for high-speed interfaces. His focus areas include high-speed system power delivery, on-chip power delivery, and Signal/ Power Integrity co-design. Prior to Intel he worked at Hughes Network Systems on Electromagnetic Interference (EMI), Electromagnetic Compatibility (EMC), power integrity, and signal integrity technologies. He has received a B.E. (Instrumentation) from College of Engineering, Pune, India, an M.S. (Electrical Engineering) from University of Utah, USA, and an Advanced Certificate for Post-Master’s Study (Computer Science) from Johns Hopkins University, USA. He is a senior member of IEEE and a member of the CPMT Technical Committee on Electrical Design, Modeling and Simulation; and he serves as a technical program committee member for DesignCon. He was a recipient of the International Engineering Consortium’s paper awards for DesignCon 2008 and DesignCon 2009.
Woong Hwan Ryu is currently a Signal/Power Integrity Engineering Manager at Intel Corporation. He has been responsible for pre-silicon signal integrity and power integrity analysis for high speed interfaces. He received his Ph.D. degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST). Dr. Ryu holds an IEEE Senior Member status; he serves as a reviewer for several IEEE journals; and he serves as a technical program committee member and organizing committee member for DesignCon. He was a recipient of the International Engineering Consortium’s paper awards for DesignCon 2006 and DesignCon 2008. Dr. Ryu has authored and co-authored more than 80 technical publications in premier journals and international conferences, and holds three issued patents and has one patent pending.
Myoung Joon Choi is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing methodologies for high-speed interface simulation and analysis. His focus areas include high-speed system SI-PI co-simulation, on-chip signal and power integrity, and computational analysis of entire high-speed systems. Dr. Choi has received a Ph.D. and an M.S. from University of Illinois at Urbana-Champaign, Urbana, IL, USA, and a BS from Korea University, Seoul, Korea. He has authored and co-authored many technical publications in journals and conferences.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success - Brian Bailey.
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