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A modeling approach for power integrity simulation in 3D-IC designs
Vinayakam Subramanian and Jairam Sukumar
4/27/2012 10:10 AM EDT
Abstract
Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.
Understanding multi-die system analysis
Power grid analysis of SoCs is a well-addressed problem that includes board and package parasitic components appended to the SoCs power delivery network (PDN). Growing integration requirements now call for 3D systems involving integration of multiple silicon die stacked inside a single package and interconnected between each other by TSV technology. The design of 3D SoC systems also requires the implementation of power distribution networks across the die.
The challenge for analysis lies in creating an integrated network extracted from multiple physical structures across the third dimension. Creating a standard modeling interface allowing seamless integration of these structures is equally critical since the die may be provided by multiple vendors who may not share their layout details, so the modeling approach and the interface definition become very critical. By using an existing chip power model solution for 3D SoC power grid elements that addresses these challenges, a modeling approach can still retain the accuracy of both static and dynamic analysis.
There are two key points for multi-die system analysis to consider. First, concurrent extraction significantly increases the capacity requirements for power grid extraction, assuming the layout for each SoC forming part of the 3D system is available for analysis. Second, a model-based approach should capture current signatures at entry and exit points as in the case of an exact scenario, to enable accurate analysis. Analysis accuracy should also be valid for both static and dynamic IR analysis.
In the 3D power flow diagram, a power analysis methodology requires an overall integration approach pertaining to layout details of power networks for multiple die. Individual layout details for the SoC are captured as standard LEF/DEF formats. The TSV is a 3D structure, so its construction related details cannot be represented in a 2D format. For IR analysis, a simple lumped parasitic model can be deployed.
Consequently, a chain of TSV networked power grids can be extracted through a standard 2D power grid extraction solution. Package parasitics are integrated at the various ball out locations of the bottom die. This part of the model integration pertains to a standard 2D analysis design flow. The following figure illustrates the concept for the interconnection of two SoC layout scenarios.
Next: A modeling approach
Designing reliable three-dimensional (3D) system-on-chips (SoCs) is extremely complex, and critical for the next level of integration in silicon design. In 3D integrated circuit (3D-IC) vertical stacked-die architecture, individual die are connected directly by Through-Silicon-Vias (TSVs) and micro-bumps. Simulation of 3D-ICs for power integrity needs to model the 3D structure, including all the ICs and their TSV interconnects. Some challenges include modeling and integrating third-party application SoCs or memories into the current design framework and performing a complete analysis. This article outlines an approach for concurrent analysis of the 3D-IC power grid, as well as a chip model-based analysis, and how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits.
Understanding multi-die system analysis
Power grid analysis of SoCs is a well-addressed problem that includes board and package parasitic components appended to the SoCs power delivery network (PDN). Growing integration requirements now call for 3D systems involving integration of multiple silicon die stacked inside a single package and interconnected between each other by TSV technology. The design of 3D SoC systems also requires the implementation of power distribution networks across the die.
The challenge for analysis lies in creating an integrated network extracted from multiple physical structures across the third dimension. Creating a standard modeling interface allowing seamless integration of these structures is equally critical since the die may be provided by multiple vendors who may not share their layout details, so the modeling approach and the interface definition become very critical. By using an existing chip power model solution for 3D SoC power grid elements that addresses these challenges, a modeling approach can still retain the accuracy of both static and dynamic analysis.
Various 3D Stack Configurations
There are two key points for multi-die system analysis to consider. First, concurrent extraction significantly increases the capacity requirements for power grid extraction, assuming the layout for each SoC forming part of the 3D system is available for analysis. Second, a model-based approach should capture current signatures at entry and exit points as in the case of an exact scenario, to enable accurate analysis. Analysis accuracy should also be valid for both static and dynamic IR analysis.
Power Flow in a 3D SoC System
In the 3D power flow diagram, a power analysis methodology requires an overall integration approach pertaining to layout details of power networks for multiple die. Individual layout details for the SoC are captured as standard LEF/DEF formats. The TSV is a 3D structure, so its construction related details cannot be represented in a 2D format. For IR analysis, a simple lumped parasitic model can be deployed.
Consequently, a chain of TSV networked power grids can be extracted through a standard 2D power grid extraction solution. Package parasitics are integrated at the various ball out locations of the bottom die. This part of the model integration pertains to a standard 2D analysis design flow. The following figure illustrates the concept for the interconnection of two SoC layout scenarios.
Concurrent Analysis Set-up
Next: A modeling approach
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